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2022-05-06target/xtensa: implement cache test option opcodesMax Filippov1-0/+38
2022-05-06tests/tcg/xtensa: fix vectors and checks in timer testMax Filippov1-7/+41
2022-05-06tests/tcg/xtensa: enable mmu tests for MMUv3Max Filippov1-79/+103
2022-05-06tests/tcg/xtensa: enable autorefill phys_mem tests for MMUv3Max Filippov1-1/+9
2022-05-06tests/tcg/xtensa: remove dependency on the loop optionMax Filippov1-10/+10
2022-05-06tests/tcg/xtensa: fix watchpoint testMax Filippov1-40/+46
2022-05-06tests/tcg/xtensa: restore vecbase SR after testMax Filippov1-0/+2
2022-05-06tests/tcg/xtensa: fix build for cores without windowed registersMax Filippov1-0/+2
2022-05-06hw/xtensa: fix reset value of MIROUT register of MX PICMax Filippov1-1/+1
2022-05-06target/xtensa: add clock input to xtensa CPUMax Filippov3-3/+24
2022-05-06target/xtensa: import core lx106Simon Safar5-0/+8273
2022-05-06target/xtensa: use tcg_constant_* for remaining opcodesMax Filippov1-52/+25
2022-05-06target/xtensa: use tcg_constant_* for FPU conversion opcodesMax Filippov1-12/+6
2022-05-06target/xtensa: use tcg_constant_* for numbered special registersMax Filippov1-12/+4
2022-05-06target/xtensa: use tcg_constant_* for TLB opcodesMax Filippov1-8/+4
2022-05-06target/xtensa: use tcg_constant_* for exceptionsMax Filippov1-13/+5
2022-05-06target/xtensa: use tcg_contatnt_* for numeric literalsMax Filippov1-19/+9
2022-05-06target/xtensa: fix missing tcg_temp_free in gen_window_checkMax Filippov1-2/+2
2022-05-05Merge tag 'pull-ppc-20220505' of https://gitlab.com/danielhb/qemu into stagingRichard Henderson20-234/+260
2022-05-05target/ppc: Change MSR_* to follow POWER ISA numbering conventionVíctor Colombo1-43/+44
2022-05-05target/ppc: Add unused msr bits FIELDsVíctor Colombo1-0/+25
2022-05-05target/ppc: Remove msr_de macroVíctor Colombo2-4/+3
2022-05-05target/ppc: Remove msr_hv macroVíctor Colombo6-17/+20
2022-05-05target/ppc: Remove msr_ts macroVíctor Colombo3-4/+4
2022-05-05target/ppc: Remove msr_fe0 and msr_fe1 macrosVíctor Colombo2-14/+15
2022-05-05target/ppc: Remove msr_ep macroVíctor Colombo2-3/+3
2022-05-05target/ppc: Remove msr_dr macroVíctor Colombo3-7/+8
2022-05-05target/ppc: Remove msr_ir macroVíctor Colombo3-7/+8
2022-05-05target/ppc: Remove msr_cm macroVíctor Colombo3-3/+3
2022-05-05target/ppc: Remove msr_fp macroVíctor Colombo2-7/+13
2022-05-05target/ppc: Remove msr_gs macroVíctor Colombo3-4/+4
2022-05-05target/ppc: Remove msr_me macroVíctor Colombo2-7/+7
2022-05-05target/ppc: Remove msr_pow macroVíctor Colombo3-8/+8
2022-05-05target/ppc: Remove msr_ce macroVíctor Colombo2-2/+2
2022-05-05target/ppc: Remove msr_ee macroVíctor Colombo4-8/+14
2022-05-05target/ppc: Remove msr_ile macroVíctor Colombo1-2/+2
2022-05-05target/ppc: Remove msr_ds macroVíctor Colombo2-2/+2
2022-05-05target/ppc: Remove msr_le macroVíctor Colombo4-11/+11
2022-05-05target/ppc: Remove msr_pr macroVíctor Colombo8-23/+30
2022-05-05target/ppc: Remove unused msr_* macrosVíctor Colombo1-20/+0
2022-05-05target/ppc: Remove fpscr_* macros from cpu.hVíctor Colombo3-44/+15
2022-05-05ppc/xive: Update the state of the External interrupt signalFrederic Barrat3-0/+17
2022-05-05ppc/xive: Always recompute the PIPR when pushing an OS contextFrederic Barrat2-10/+17
2022-05-05vhost-user: Use correct macro name TARGET_PPC64Murilo Opsfelder Araujo1-1/+1
2022-05-05target/ppc: Fix BookE debug interrupt generationBin Meng1-2/+2
2022-05-05target/ppc: init 'rmmu_info' in kvm_get_radix_page_info()Daniel Henrique Barboza1-1/+1
2022-05-05target/ppc: init 'sregs' in kvmppc_put_books_sregs()Daniel Henrique Barboza1-1/+1
2022-05-05target/ppc: init 'lpcr' in kvmppc_enable_cap_large_decr()Daniel Henrique Barboza1-1/+1
2022-05-05target/ppc: initialize 'val' union in kvm_get_one_spr()Daniel Henrique Barboza1-1/+2
2022-05-05Merge tag 'pull-target-arm-20220505' of https://git.linaro.org/people/pmaydel...Richard Henderson21-661/+735
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