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2022-09-27vfio/migration: Fix incorrect initialization value for parameters in VFIOMigr...Kunkun Jiang1-0/+2
2022-09-27Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into stagingStefan Hajnoczi4-50/+157
2022-09-27Merge tag 'm68k-for-7.2-pull-request' of https://github.com/vivier/qemu-m68k ...Stefan Hajnoczi4-10/+19
2022-09-27Merge tag 'pull-request-2022-09-26' of https://gitlab.com/thuth/qemu into sta...Stefan Hajnoczi53-269/+1287
2022-09-27Merge tag 'kraxel-20220927-pull-request' of https://gitlab.com/kraxel/qemu in...Stefan Hajnoczi31-205/+903
2022-09-27Merge tag 'pull-riscv-to-apply-20220927' of https://github.com/alistair23/qem...Stefan Hajnoczi22-282/+531
2022-09-27virtio: del net client if net_init_tap_one failedlu zhipeng1-6/+12
2022-09-27vdpa: Allow MQ feature in SVQEugenio Pérez1-0/+1
2022-09-27virtio-net: Update virtio-net curr_queue_pairs in vdpa backendsEugenio Pérez1-11/+6
2022-09-27vdpa: validate MQ CVQ commandsEugenio Pérez1-0/+9
2022-09-27vdpa: Add vhost_vdpa_net_load_mqEugenio Pérez1-0/+26
2022-09-27vdpa: extract vhost_vdpa_net_load_mac from vhost_vdpa_net_loadEugenio Pérez1-22/+40
2022-09-27vdpa: Make VhostVDPAState cvq_cmd_in_buffer control ack typeEugenio Pérez1-11/+12
2022-09-27e1000e: set RX desc status with DD flag in a separate operationDing Hui1-1/+52
2022-09-27virtio-gpu: update scanout if there is any area covered by the rectDongwon Kim1-3/+4
2022-09-27hw/display/ati_2d: Fix buffer overflow in ati_2d_blt (CVE-2021-3638)Philippe Mathieu-Daudé1-3/+3
2022-09-27audio: remove abort() in audio_bug()Volker Rümelin1-1/+0
2022-09-27Revert "audio: Log context for audio bug"Volker Rümelin2-24/+28
2022-09-27audio: Add sndio backendAlexandre Ratchov10-5/+632
2022-09-27usbnet: Report link-up via interrupt endpoint in CDC-ECM modeMichael Brown1-6/+21
2022-09-27usbnet: Detect short packets as sent by the xHCI controllerMichael Brown1-1/+1
2022-09-27usbnet: Accept mandatory USB_CDC_SET_ETHERNET_PACKET_FILTER requestMichael Brown1-0/+6
2022-09-27usbnet: Add missing usb_wakeup() call in usbnet_receive()Michael Brown1-0/+3
2022-09-27hcd-xhci: drop operation with secondary stream arrays enabledQiang Liu1-1/+3
2022-09-27usb/msd: add usb_msd_fatal_error() and fix guest-triggerable assertGerd Hoffmann3-1/+31
2022-09-27usb/msd: move usb_msd_packet_complete()Gerd Hoffmann1-12/+14
2022-09-27target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unorderedYang Liu4-15/+31
2022-09-27target/riscv: rvv-1.0: Simplify vfwredsum codeYang Liu1-46/+10
2022-09-27target/riscv: debug: Add initial support of type 6 triggerFrank Chang2-4/+188
2022-09-27target/riscv: debug: Check VU/VS modes for type 2 triggerFrank Chang1-0/+10
2022-09-27target/riscv: debug: Create common trigger actions functionFrank Chang2-2/+70
2022-09-27target/riscv: debug: Introduce tinfo CSRFrank Chang4-3/+18
2022-09-27target/riscv: debug: Restrict the range of tselect value can be writtenFrank Chang1-6/+3
2022-09-27target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRsFrank Chang4-88/+48
2022-09-27target/riscv: debug: Introduce build_tdata1() to build tdata1 register contentFrank Chang2-5/+12
2022-09-27target/riscv: debug: Determine the trigger type from tdata1.typeFrank Chang5-67/+140
2022-09-26m68k: align bootinfo strings and data to 4 bytesJason A. Donenfeld1-4/+6
2022-09-26target/m68k: use M68K_FEATURE_MOVEFROMSR_PRIV feature for move_from_sr privil...Mark Cave-Ayland3-1/+8
2022-09-26target/m68k: increase size of m68k CPU features from uint32_t to uint64_tMark Cave-Ayland2-5/+5
2022-09-27hw/riscv/sifive_e: Fix inheritance of SiFiveEStateBernhard Beschow1-1/+2
2022-09-27target/riscv: Check the correct exception cause in vector GDB stubFrank Chang1-2/+2
2022-09-27hw/riscv: opentitan: Expose the resetvec as a SoC propertyAlistair Francis2-1/+9
2022-09-27hw/riscv: opentitan: Fixup resetvecAlistair Francis1-1/+1
2022-09-27target/riscv: Set the CPU resetvec directlyAlistair Francis3-15/+7
2022-09-27target/riscv: remove fixed numbering from GDB xml feature filesAndrew Burgess4-20/+4
2022-09-27target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xmlAndrew Burgess3-38/+2
2022-09-27target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h}Weiwei Li1-4/+9
2022-09-27target/riscv: Remove sideleg and sedelegRahul Pathak2-4/+0
2022-09-27docs/system: clean up code escape for riscv virt platformAlex Bennée1-4/+9
2022-09-27hw/ssi: ibex_spi: update reg addrWilfred Mallawa1-1/+1