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2023-01-05tcg: Introduce tcg_type_sizeRichard Henderson2-15/+28
Add a helper function for computing the size of a type. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-05tcg: Move TCG_TYPE_COUNT outside enumRichard Henderson1-1/+2
The count is not itself an enumerator. Move it outside to prevent the compiler from considering it with -Wswitch-enum. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-05tcg: Allocate TCGTemp pairs in host memory orderRichard Henderson2-32/+30
Allocate the first of a pair at the lower address, and the second of a pair at the higher address. This will make it easier to find the beginning of the larger memory block. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-05tcg: Simplify calls to temp_sync vs mem_coherentRichard Henderson1-6/+2
The first thing that temp_sync does is check mem_coherent, so there's no need for the caller to do so. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-05tcg: Add temp_subindex to TCGTempRichard Henderson2-0/+4
Record the location of a TCGTemp within a larger object. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-05tcg: Move TCG_{LOW,HIGH} to tcg-internal.hRichard Henderson5-49/+49
Move the error-generating fallback from tcg-op.c, and replace "_link_error" with modern QEMU_ERROR markup. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-05target/sparc: Avoid TCGV_{LOW,HIGH}Richard Henderson1-17/+4
Use the official extend/extract functions instead of routines that will shortly be internal to tcg. Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-05accel/tcg: Set cflags_next_tb in cpu_common_initfnRichard Henderson1-0/+1
While we initialize this value in cpu_common_reset, that isn't called during startup, so set it as well in init. This fixes -singlestep versus the very first TB. Fixes: 04f5b647ed07 ("accel/tcg: Handle -singlestep in curr_cflags") Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-05tcg: Introduce paired register allocationRichard Henderson2-44/+374
There are several instances where we need to be able to allocate a pair of registers to related inputs/outputs. Add 'p' and 'm' register constraints for this, in order to be able to allocate the even/odd register first or second. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-04tcg: Massage process_op_defs()Philippe Mathieu-Daudé1-27/+34
In preparation of introducing paired registers, massage a bit process_op_defs()'s switch case. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> [PMD: Split from bigger patch, 1/3] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221219220925.79218-2-philmd@linaro.org>
2023-01-04tcg: Remove check_regsRichard Henderson1-76/+0
We now check the consistency of reg_to_temp[] with each update, so the utility of checking consistency at the end of each opcode is minimal. In addition, the form of this check is quite expensive, consuming 10% of a checking-enabled build. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-04tcg: Centralize updates to reg_to_tempRichard Henderson1-74/+85
Create two new functions, set_temp_val_{reg,nonreg}. Assert that the reg_to_temp mapping is correct before any changes are made. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-04tcg: Fix tcg_reg_alloc_dup*Richard Henderson1-2/+2
The assignment to mem_coherent should be done with any modification, not simply with a newly allocated register. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-04tci: MAX_OPC_PARAM_IARGS is no longer usedRichard Henderson2-5/+0
Unused since commit 7b7d8b2d9a ("tcg/tci: Use ffi for calls"). Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-04tcg: Remove TCG_TARGET_STACK_GROWSUPRichard Henderson3-32/+2
The hppa host code has been removed since 2013; this should have been deleted at the same time. Fixes: 802b5081233a ("tcg-hppa: Remove tcg backend") Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-04tcg: Tidy tcg_reg_alloc_opRichard Henderson1-24/+21
Replace goto allocate_in_reg with a boolean. Remove o_preferred_regs which isn't used, except to copy. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-04accel/tcg: Use QEMU_IOTHREAD_LOCK_GUARD in io_readx/io_writexRichard Henderson1-17/+8
Narrow the scope of the lock to the actual read/write, moving the cpu_transation_failed call outside the lock. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-04hw/ppc: Use QEMU_IOTHREAD_LOCK_GUARD in ppc_set_irqRichard Henderson1-9/+1
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-04target/riscv: Use QEMU_IOTHREAD_LOCK_GUARD in riscv_cpu_update_mipRichard Henderson1-9/+1
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-04target/ppc: Use QEMU_IOTHREAD_LOCK_GUARD in cpu_interrupt_exittbRichard Henderson1-10/+4
In addition, use tcg_enabled instead of !kvm_enabled. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-04target/ppc: Use QEMU_IOTHREAD_LOCK_GUARD in ppc_maybe_interruptRichard Henderson1-10/+1
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-04hw/mips: Use QEMU_IOTHREAD_LOCK_GUARD in cpu_mips_irq_requestRichard Henderson1-10/+1
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-04qemu/main-loop: Introduce QEMU_IOTHREAD_LOCK_GUARDRichard Henderson1-0/+29
Create a wrapper for locking/unlocking the iothread lock. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-04tcg: Cleanup trailing whitespaceRichard Henderson2-17/+18
Remove whitespace at end of line, plus one place this also highlights some missing braces. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-04tcg/s390x: Fix coding stylePhilippe Mathieu-Daudé1-10/+10
We are going to modify this code, so fix its style first to avoid: ERROR: spaces required around that '*' (ctx:VxV) #281: FILE: tcg/s390x/tcg-target.c.inc:1224: + uintptr_t mask = ~(0xffffull << i*16); ^ Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221130132654.76369-2-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-04meson: Move CONFIG_TCG_INTERPRETER to config_hostRichard Henderson1-3/+1
Like CONFIG_TCG, the enabled method of execution is a host property not a guest property. This exposes the define to compile-once files. Acked-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-04tcg: convert tcg/README to rstMark Cave-Ayland5-785/+945
Convert tcg/README to rst and move it to docs/devel as a new "TCG Intermediate Representation" page. There are a few minor changes to improve the aesthetic of the final output which are as follows: - Rename the title from "Tiny Code Generator - Fabrice Bellard" to "TCG Intermediate Representation" - Remove the section numbering - Add the missing parameters to the ssadd_vec operations in the "Host vector operations" section - Change the path to the Atomic Operations document to use a proper reference - Replace tcg/README in tcg.rst with a proper reference to the new document Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Fabiano Rosas <farosas@suse.de> Message-Id: <20221130100434.64207-2-mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-04.gitlab-ci.d/windows: Work-around timeout and OpenGL problems of the MSYS2 jobsThomas Huth1-3/+4
The windows jobs (especially the 32-bit job) recently started to hit the timeout limit. Bump it a little bit to ease the situation (80 minutes is quite long already - OTOH, these jobs do not have to wait for a job from the container stage to finish, so this should still be OK). Additionally, some update on the container side recently enabled OpenGL in these jobs - but the corresponding code fails to compile. Thus disable OpenGL here for the time being until someone figured out the proper fix in the shader code for this. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-id: 20230104123559.277586-1-thuth@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-04Merge tag 'pull-testing-next-231222-1' of https://gitlab.com/stsquad/qemu ↵Peter Maydell11-227/+47
into staging testing updates: - fix minor shell-ism that can break check-tcg - turn off verbose logging on custom runners - make configure echo call in CI - fix unused variable in linux-test - add binary compiler docker image for hexagon - disable doc and gui builds for tci and disable-tcg builds # gpg: Signature made Fri 23 Dec 2022 15:18:41 GMT # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * tag 'pull-testing-next-231222-1' of https://gitlab.com/stsquad/qemu: gitlab-ci: Disable docs and GUIs for the build-tci and build-tcg-disabled jobs tests/docker: use prebuilt toolchain for debian-hexagon-cross tests/tcg: fix unused variable in linux-test configure: repeat ourselves for the benefit of CI gitlab: turn off verbose logging for make check on custom runners configure: Fix check-tcg not executing any tests Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-04Merge tag 'pull-9p-20221223' of https://github.com/cschoenebeck/qemu into ↵Peter Maydell5-38/+37
staging 9pfs: Windows host prep, cleanup * Next preparatory patches for upcoming Windows host support. * Cleanup patches. # gpg: Signature made Fri 23 Dec 2022 11:04:26 GMT # gpg: using RSA key 96D8D110CF7AF8084F88590134C2B58765A47395 # gpg: issuer "qemu_oss@crudebyte.com" # gpg: Good signature from "Christian Schoenebeck <qemu_oss@crudebyte.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: ECAB 1A45 4014 1413 BA38 4926 30DB 47C3 A012 D5F4 # Subkey fingerprint: 96D8 D110 CF7A F808 4F88 5901 34C2 B587 65A4 7395 * tag 'pull-9p-20221223' of https://github.com/cschoenebeck/qemu: hw/9pfs: Replace the direct call to xxxat() APIs with a wrapper hw/9pfs: Drop unnecessary *xattr wrapper API declarations qemu/xattr.h: Exclude <sys/xattr.h> for Windows MAINTAINERS: Add 9p test client to section "virtio-9p" 9pfs: Fix some return statements in the synth backend Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-12-23gitlab-ci: Disable docs and GUIs for the build-tci and build-tcg-disabled jobsThomas Huth1-2/+4
These jobs use their own "script:" section and thus do not profit from the global "--disable-docs" from the template. While we're at it, disable also some GUI front ends here since we do not gain any additional test coverage by compiling those here again. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20221208135945.99975-1-thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221221090411.1995037-7-alex.bennee@linaro.org>
2022-12-23tests/docker: use prebuilt toolchain for debian-hexagon-crossMukilan Thiyagarajan6-205/+20
The current docker image for cross compiling hexagon guests is manually built since it takes >2 hours to build from source. This patch: 1. Solves the above issue by using the prebuilt clang toolchain hosted on CodeLinaro [1] and maintained by QUIC [2]. 2. The dockerfile is also switched from multi-stage to single stage build to allow the CI docker engine to reuse the layer cache. 3. Re-enables the hexagon-cross-container job to be always run in CI and makes it a non-optional dependency for the build-user-hexagon job. The changes for 1 & 2 together bring down the build time to ~3 minutes in GitLab CI when cache is reused and ~9 minutes when cache cannot be reused. [1]: https://github.com/CodeLinaro/hexagon-builder [2]: https://github.com/quic/toolchain_for_hexagon/releases/ Signed-off-by: Mukilan Thiyagarajan <quic_mthiyaga@quicinc.com> [AJB: also tweak MAINTAINERS, remove QEMU_JOB_ONLY_FORKS and comment] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20221219144354.11659-1-quic_mthiyaga@quicinc.com> Message-Id: <20221221090411.1995037-6-alex.bennee@linaro.org>
2022-12-23tests/tcg: fix unused variable in linux-testAlex Bennée1-1/+5
The latest hexagon compiler picks up that we never consume wcount. Given the name of the #define that rcount checks against is WCOUNT_MAX I figured the check just got missed. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221221090411.1995037-5-alex.bennee@linaro.org>
2022-12-23configure: repeat ourselves for the benefit of CIAlex Bennée1-3/+4
Our CI system echos the lines it executes but not the expansions. For the sake of a line of extra verbosity during the configure phase lets echo the invocation of script to stdout as well as the log when on CI. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221221090411.1995037-4-alex.bennee@linaro.org>
2022-12-23gitlab: turn off verbose logging for make check on custom runnersAlex Bennée3-13/+13
The verbosity adds a lot of unnecessary output to the CI logs which end up getting truncated anyway. We can always extract information from the meson test logs on a failure and for the custom runners its generally easier to re-create failures anyway. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20221221090411.1995037-3-alex.bennee@linaro.org>
2022-12-23configure: Fix check-tcg not executing any testsMukilan Thiyagarajan1-3/+1
After configuring with --target-list=hexagon-linux-user running `make check-tcg` just prints the following: ``` make: Nothing to be done for 'check-tcg' ``` In the probe_target_compiler function, the 'break' command is used incorrectly. There are no lexically enclosing loops associated with that break command which is an unspecfied behaviour in the POSIX standard. The dash shell implementation aborts the currently executing loop, in this case, causing the rest of the logic for the loop in line 2490 to be skipped, which means no Makefiles are generated for the tcg target tests. Fixes: c3b570b5a9a24d25 (configure: don't enable cross compilers unless in target_list) Signed-off-by: Mukilan Thiyagarajan <quic_mthiyaga@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Link: https://patchew.org/QEMU/20221207082309.9966-1-quic._5Fmthiyaga@quicinc.com/ Message-Id: <20221207082309.9966-1-quic_mthiyaga@quicinc.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20221221090411.1995037-2-alex.bennee@linaro.org>
2022-12-23hw/9pfs: Replace the direct call to xxxat() APIs with a wrapperBin Meng2-20/+27
xxxat() APIs are only available on POSIX platforms. For future extension to Windows, let's replace the direct call to xxxat() APIs with a wrapper. Signed-off-by: Bin Meng <bin.meng@windriver.com> Message-Id: <20221219102022.2167736-4-bin.meng@windriver.com> Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
2022-12-23hw/9pfs: Drop unnecessary *xattr wrapper API declarationsBin Meng1-11/+0
These are not used anywhere in the source tree. Drop them. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Greg Kurz <groug@kaod.org> Message-Id: <20221219102022.2167736-3-bin.meng@windriver.com> Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
2022-12-23qemu/xattr.h: Exclude <sys/xattr.h> for WindowsBin Meng1-1/+3
Windows does not have <sys/xattr.h>. Signed-off-by: Bin Meng <bin.meng@windriver.com> Message-Id: <20221219102022.2167736-2-bin.meng@windriver.com> Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
2022-12-23MAINTAINERS: Add 9p test client to section "virtio-9p"Christian Schoenebeck1-0/+1
The 9p test cases use a dedicated, lite-weight 9p client implementation (using virtio transport) under tests/qtest/libqos/ to communicate with QEMU's 9p server. It's already there for a long time. Let's officially assign it to 9p maintainers. Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Message-Id: <E1ozhlV-0007BU-0g@lizzy.crudebyte.com>
2022-12-239pfs: Fix some return statements in the synth backendGreg Kurz1-6/+6
The qemu_v9fs_synth_mkdir() and qemu_v9fs_synth_add_file() functions currently return a positive errno value on failure. This causes checkpatch.pl to spit several errors like the one below: ERROR: return of an errno should typically be -ve (return -EAGAIN) + return EAGAIN; Simply change the sign. This has no consequence since callers assert() the returned value to be equal to 0. Reported-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <166930551818.827792.10663674346122681963.stgit@bahia> [C.S.: - Resolve conflict with 66997c42e02c. ] Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
2022-12-21Merge tag 'pull-ppc-20221221' of https://gitlab.com/danielhb/qemu into stagingPeter Maydell20-34/+220
ppc patch queue for 2022-12-21: This queue contains a MAINTAINERS update, the implementation of the Freescale eSDHC, the introduction of the DEXCR/HDEXCR instructions and other assorted fixes (most of them for the e500 board). # gpg: Signature made Wed 21 Dec 2022 17:18:53 GMT # gpg: using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164 # gpg: issuer "danielhb413@gmail.com" # gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 17EB FF99 23D0 1800 AF28 3819 3CD9 CA96 DE03 3164 * tag 'pull-ppc-20221221' of https://gitlab.com/danielhb/qemu: target/ppc: Check DEXCR on hash{st, chk} instructions target/ppc: Implement the DEXCR and HDEXCR hw/ppc/e500: Move comment to more appropriate place hw/ppc/e500: Resolve variable shadowing hw/ppc/e500: Prefer local variable over qdev_get_machine() hw/ppc/virtex_ml507: Prefer local over global variable target/ppc/mmu_common: Fix table layout of "info tlb" HMP command target/ppc/mmu_common: Log which effective address had no TLB entry found hw/ppc/spapr: Reduce "vof.h" inclusion hw/ppc/vof: Do not include the full "cpu.h" target/ppc/kvm: Add missing "cpu.h" and "exec/hwaddr.h" hw/ppc/e500: Add Freescale eSDHC to e500plat hw/sd/sdhci: Support big endian SD host controller interfaces MAINTAINERS: downgrade PPC KVM/TCG CPUs and pSeries to 'Odd Fixes' Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-12-21target/ppc: Check DEXCR on hash{st, chk} instructionsNicholas Miehlbradt1-15/+43
Adds checks to the hashst and hashchk instructions to only execute if enabled by the relevant aspect in the DEXCR and HDEXCR. This behaviour is guarded behind TARGET_PPC64 since Power10 is currently the only implementation which has the DEXCR. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Nicholas Miehlbradt <nicholas@linux.ibm.com> Message-Id: <20221220042330.2387944-3-nicholas@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-12-21target/ppc: Implement the DEXCR and HDEXCRNicholas Miehlbradt4-0/+64
Define the DEXCR and HDEXCR as special purpose registers. Each register occupies two SPR indicies, one which can be read in an unprivileged state and one which can be modified in the appropriate priviliged state, however both indicies refer to the same underlying value. Note that the ISA uses the abbreviation UDEXCR in two different contexts: the userspace DEXCR, the SPR index which can be read from userspace (implemented in this patch), and the ultravisor DEXCR, the equivalent register for the ultravisor state (not implemented). Signed-off-by: Nicholas Miehlbradt <nicholas@linux.ibm.com> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20221220042330.2387944-2-nicholas@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-12-21hw/ppc/e500: Move comment to more appropriate placeBernhard Beschow1-1/+1
The TLB entries are set up in mmubooke_create_initial_mapping(), not in booke206_page_size_to_tlb(). Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20221216145709.271940-7-shentey@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-12-21hw/ppc/e500: Resolve variable shadowingBernhard Beschow1-3/+1
Assign to the outer variable instead which even saves some code. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20221216145709.271940-6-shentey@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-12-21hw/ppc/e500: Prefer local variable over qdev_get_machine()Bernhard Beschow1-3/+2
Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221216145709.271940-5-shentey@gmail.com> [danielhb: remove linebreak in object_property_add_child()] Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-12-21hw/ppc/virtex_ml507: Prefer local over global variableBernhard Beschow1-1/+1
Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221216145709.271940-4-shentey@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-12-21target/ppc/mmu_common: Fix table layout of "info tlb" HMP commandBernhard Beschow1-1/+1
Starting with the URWX columns the columns didn't line up. Before: QEMU 7.2.50 monitor - type 'help' for more information (qemu) info tlb TLB0: Effective Physical Size TID TS SRWX URWX WIMGE U0123 0x0000000000a80000 0x000000000105d000 4K 117 0 SR--UR-- --M-- U---- 0x0000000000100000 0x000000000114e000 4K 117 0 SR--UR-- --M-- U---- <snip TLB1: Effective Physical Size TID TS SRWX URWX WIMGE U0123 0x00000000c0000000 0x0000000000000000 16M 0 0 SR-XU--- --M-- U---- 0x00000000c1000000 0x0000000001000000 16M 0 0 SRW-U--- --M-- U---- <snip> (qemu) After: QEMU 7.2.50 monitor - type 'help' for more information (qemu) info tlb TLB0: Effective Physical Size TID TS SRWX URWX WIMGE U0123 0x00000000b7a00000 0x000000000fcf5000 4K 18 0 SR-- UR-- --M-- U---- 0x0000000000800000 0x000000000fd73000 4K 18 0 SR-- UR-X --M-- U---- <snip> TLB1: Effective Physical Size TID TS SRWX URWX WIMGE U0123 0x00000000c0000000 0x0000000000000000 16M 0 0 SR-X U--- --M-- U---- 0x00000000c1000000 0x0000000001000000 16M 0 0 SRW- U--- --M-- U---- <snip> (qemu) Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221216145709.271940-3-shentey@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-12-21target/ppc/mmu_common: Log which effective address had no TLB entry foundBernhard Beschow1-1/+2
Let's not leave developers in the dark where this log message comes from. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221216145709.271940-2-shentey@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
generated by cgit v1.1 at 2025-01-31 04:54:04 +0000