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2021-06-03target/arm: Fix return values in fp_sysreg_checks()Peter Maydell1-3/+3
The fp_sysreg_checks() function is supposed to be returning an FPSysRegCheckResult, which is an enum with three possible values. However, three places in the function "return false" (a hangover from a previous iteration of the design where the function just returned a bool). Make these return FPSysRegCheckFailed instead (for no functional change, since both false and FPSysRegCheckFailed are zero). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210520152840.24453-6-peter.maydell@linaro.org
2021-06-03target/arm: Add MVE check to VMOV_reg_sp and VMOV_reg_dpPeter Maydell1-2/+13
Split out the handling of VMOV_reg_sp and VMOV_reg_dp so that we can permit the insns if either FP or MVE are present. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210520152840.24453-5-peter.maydell@linaro.org
2021-06-03target/arm: Move fpsp/fpdp isar check into callers of do_vfp_2op_sp/dpPeter Maydell1-18/+19
The do_vfp_2op_sp() and do_vfp_2op_dp() functions currently check whether floating point is supported via the aa32_fpdp_v2 and aa32_fpsp_v2 isar checks. For v8.1M MVE support, the VMOV_reg trans functions (but not any of the others) need to update this to also allow the insn if MVE is implemented. Move the check out of the do_ function and into its callsites (which are all implemented via the DO_VFP_2OP macro), so we have a place to change the check for the VMOV insns. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210520152840.24453-4-peter.maydell@linaro.org
2021-06-03target/arm: Update feature checks for insns which are "MVE or FP"Peter Maydell1-19/+29
Some v8M instructions are present if either the floating point extension or MVE is implemented. Update our implementation of them to check for MVE as well as for FP. This is all the insns which use CheckDecodeFaults(ExtType_MveOrFp) or CheckDecodeFaults(ExtType_MveOrDpFp) in their pseudocode, which are essentially the loads and stores, moves and sysreg accesses, except for VMOV_reg_sp and VMOV_reg_dp, which we handle in subsequent patches because they need a refactor to provide a place to put the new MVE check. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210520152840.24453-3-peter.maydell@linaro.org
2021-06-03target/arm: Add isar feature check functions for MVEPeter Maydell1-0/+22
Add the isar feature check functions we will need for v8.1M MVE: * a check for MVE present: this corresponds to the pseudocode's CheckDecodeFaults(ExtType_Mve) * a check for the optional floating-point part of MVE: this corresponds to CheckDecodeFaults(ExtType_MveFp) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210520152840.24453-2-peter.maydell@linaro.org
2021-06-03Merge remote-tracking branch 'remotes/dg-gitlab/tags/ppc-for-6.1-20210603' ↵Peter Maydell33-1208/+1064
into staging ppc patch queue 2021-06-03 Next batch of ppc target patches. Highlights are: * A fix for a regression with single-step mode * Start of moving ppc to use decodetree * Implementation of some POWER10 64-bit prefixed instructions * Several cleanups to softmmu code * Continued progress towards allowing --disable-tcg * Fix for the POWER PEF implementation * Fix for LPCR handling of hotplugged CPUs * Assorted other bugfixes and cleanups This patchset does contain a couple of changes to code outside my normal scope of maintainership, related to the removal of cpu_dump and cpu_statistics hooks. ppc was the last target arch implementing these at all, and they didn't really do anything there either. The patches should have relevant acks. # gpg: Signature made Thu 03 Jun 2021 09:20:59 BST # gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full] # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full] # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full] # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown] # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dg-gitlab/tags/ppc-for-6.1-20210603: (42 commits) target/ppc: fix single-step exception regression target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree target/ppc: Move addpcis to decodetree target/ppc: Implement vcfuged instruction target/ppc: Implement cfuged instruction target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions target/ppc: Implement prefixed integer store instructions target/ppc: Move D/DS/X-form integer stores to decodetree target/ppc: Implement prefixed integer load instructions target/ppc: Move D/DS/X-form integer loads to decodetree target/ppc: Implement PNOP target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI target/ppc: Add infrastructure for prefixed insns target/ppc: Move page crossing check to ppc_tr_translate_insn target/ppc: Introduce macros to check isa extensions target/ppc: powerpc_excp: Consolidade TLB miss code target/ppc: powerpc_excp: Remove dump_syscall_vectored target/ppc: powerpc_excp: Move lpes code to where it is used target/ppc: overhauled and moved logic of storing fpscr target/ppc: removed all mentions to PPC_DUMP_CPU ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-03target/ppc: fix single-step exception regressionLuis Pires1-3/+2
Commit 6086c75 (target/ppc: Replace POWERPC_EXCP_BRANCH with DISAS_NORETURN) broke the generation of exceptions when CPU_SINGLE_STEP or CPU_BRANCH_STEP were set, due to nip always being reset to the address of the current instruction. This fix leaves nip untouched when generating the exception. Signed-off-by: Luis Pires <luis.pires@eldorado.org.br> Reported-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210602125103.332793-1-luis.pires@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetreeMatheus Ferst3-52/+45
Additionally, REQUIRE_64BIT when L=1 to match what is specified in The Programming Environments Manual: "For 32-bit implementations, the L field must be cleared, otherwise the instruction form is invalid." Some CPUs are known to deviate from this specification by ignoring the L bit [1]. The stricter behavior, however, can help users that test software with qemu, making it more likely to detect bugs that would otherwise be silent. If deemed necessary, a future patch can adapt this behavior based on the specific CPU model. [1] The 601 manual is the only one I've found that explicitly states that the L bit is ignored, but we also observe this behavior in a 7447A v1.2. Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210601193528.2533031-15-matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [dwg: Corrected whitespace error] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03target/ppc: Move addpcis to decodetreeMatheus Ferst3-9/+13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210601193528.2533031-14-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03target/ppc: Implement vcfuged instructionMatheus Ferst3-0/+64
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210601193528.2533031-13-matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03target/ppc: Implement cfuged instructionMatheus Ferst4-0/+79
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210601193528.2533031-12-matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructionsMatheus Ferst2-0/+33
Implements the following PowerISA v3.1 instructions: setbc: Set Boolean Condition setbcr: Set Boolean Condition Reverse setnbc: Set Negative Boolean Condition setnbcr: Set Negative Boolean Condition Reverse Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210601193528.2533031-11-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03target/ppc: Implement prefixed integer store instructionsRichard Henderson2-0/+16
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210601193528.2533031-10-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03target/ppc: Move D/DS/X-form integer stores to decodetreeRichard Henderson3-82/+49
These are all connected by macros in the legacy decoding. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210601193528.2533031-9-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03target/ppc: Implement prefixed integer load instructionsRichard Henderson2-0/+31
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210601193528.2533031-8-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03target/ppc: Move D/DS/X-form integer loads to decodetreeRichard Henderson3-123/+150
These are all connected by macros in the legacy decoding. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210601193528.2533031-7-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03target/ppc: Implement PNOPRichard Henderson2-0/+78
The illegal suffix behavior matches what was observed in a POWER10 DD2.0 machine. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210601193528.2533031-6-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03target/ppc: Move ADDI, ADDIS to decodetree, implement PADDIRichard Henderson4-29/+64
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210601193528.2533031-5-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03target/ppc: Add infrastructure for prefixed insnsRichard Henderson6-6/+95
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210601193528.2533031-4-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03target/ppc: Move page crossing check to ppc_tr_translate_insnRichard Henderson1-3/+6
With prefixed instructions, the number of instructions remaining until the page crossing is no longer constant. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210601193528.2533031-3-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03target/ppc: Introduce macros to check isa extensionsRichard Henderson1-0/+26
These will be used by the decodetree trans_* functions to early-exit when the instruction set is not enabled. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210601193528.2533031-2-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03target/ppc: powerpc_excp: Consolidade TLB miss codeFabiano Rosas1-35/+2
The only difference in the code for Instruction fetch, Data load and Data store TLB miss errors is that when called from an unsupported processor (i.e. not one of 602, 603, 603e, G2, 7x5 or 74xx), they abort with a message specific to the operation type (insn fetch, data load/store). If a processor does not support those interrupts we should not be registering them in init_excp_<proc> to begin with, so that error message would never be used. I'm leaving the message in for completeness, but making it generic and consolidating the three interrupts into the same case statement body. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20210601214649.785647-4-farosas@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03target/ppc: powerpc_excp: Remove dump_syscall_vectoredFabiano Rosas1-13/+1
This function is identical to dump_syscall, so use the latter for system call vectored as well. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20210601214649.785647-3-farosas@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03target/ppc: powerpc_excp: Move lpes code to where it is usedFabiano Rosas1-22/+25
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20210601214649.785647-2-farosas@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03target/ppc: overhauled and moved logic of storing fpscrBruno Larsen (billionai)4-234/+65
Followed the suggested overhaul to store_fpscr logic, and moved it to cpu.c where it can be accessed in !TCG builds. The overhaul was suggested because storing a value to fpscr should never raise an exception, so we could remove all the mess that happened with POWERPC_EXCP_FP. We also moved fpscr_set_rounding_mode into cpu.c as it could now be moved there, and it is needed when a value for the fpscr is being stored directly. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210527163522.23019-1-bruno.larsen@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03target/ppc: removed all mentions to PPC_DUMP_CPUBruno Larsen (billionai)3-312/+0
This feature will no longer be useful as ppc moves to using decodetree for TCG. And building with it enabled is no longer possible, due to changes in opc_handler_t. Since the last commit that mentions it happened in 2014, I think it is safe to remove it. Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br> Message-Id: <20210531145629.21300-5-bruno.larsen@eldorado.org.br> Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03target/ppc: removed GEN_OPCODE decision treeBruno Larsen (billionai)1-79/+0
since both, PPC_DO_STATISTICS and PPC_DUMP_CPU, are obsoleted as target/ppc moves to decodetree, we can remove this ifdef based decision tree, and only have what is now the standard option for the macro. Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br> Message-Id: <20210531145629.21300-4-bruno.larsen@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03HMP: added info cpustats to removed_features.rstBruno Larsen (billionai)1-0/+5
Documented the removal of the HMP command info cpustats Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br> Message-Id: <20210531145629.21300-3-bruno.larsen@eldorado.org.br> Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Reviewed-by: Lucas Mateus <lucas.araujo@eldorado.org.br> Reviewed-by: Greg Kurz <groug@kaod.org> [dwg: Fix a Sphinx formatting error] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03hw/core/cpu: removed cpu_dump_statistics functionBruno Larsen (billionai)2-21/+0
No more architectures set the pointer to dump_statistics, so there's no point in keeping it, or the related cpu_dump_statistics function. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br> Message-Id: <20210526202104.127910-6-bruno.larsen@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20210531145629.21300-2-bruno.larsen@eldorado.org.br> Acked-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03ppc/pef.c: initialize cgs->ready in kvmppc_svm_init()Daniel Henrique Barboza1-2/+4
QEMU is failing to launch a CGS pSeries guest in a host that has PEF support: qemu-system-ppc64: ../softmmu/vl.c:2585: qemu_machine_creation_done: Assertion `machine->cgs->ready' failed. Aborted This is happening because we're not setting the cgs->ready flag that is asserted in qemu_machine_creation_done() during machine start. cgs->ready is set in s390_pv_kvm_init() and sev_kvm_init(). Let's set it in kvmppc_svm_init() as well. Reported-by: Ram Pai <linuxram@us.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20210528201619.52363-1-danielhb413@gmail.com> Acked-by: Ram Pai <linuxram@us.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03monitor: removed cpustats commandBruno Larsen (billionai)2-24/+0
Since ppc was the last architecture to collect these statistics and it is currently phasing this collection out, the command that would query this information is being removed. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br> Message-Id: <20210526202104.127910-5-bruno.larsen@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03target/ppc: removed mentions to DO_PPC_STATISTICSBruno Larsen (billionai)1-12/+4
Removed the commented out definition and all ifdefs relating to PPC_DUMP_STATISTICS, as it's hardly ever used. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br> Message-Id: <20210526202104.127910-4-bruno.larsen@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03target/ppc: remove ppc_cpu_dump_statisticsBruno Larsen (billionai)3-55/+0
This function requires surce code modification to be useful, which means it probably is not used often, and the move to using decodetree means the statistics won't even be collected anymore. Also removed setting dump_statistics in ppc_cpu_realize, since it was only useful when in conjunction with ppc_cpu_dump_statistics. Suggested-by: Richard Henderson<richard.henderson@linaro.org> Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br> Message-Id: <20210526202104.127910-3-bruno.larsen@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03target/ppc: updated meson.build to support disable-tcgBruno Larsen (billionai)1-2/+5
updated build file to not compile some sources that are unnecessary if TCG is disabled on the system. Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br> Message-Id: <20210525115355.8254-5-bruno.larsen@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03target/ppc: created tcg-stub.c fileBruno Larsen (billionai)2-0/+49
Created a file with stubs needed to compile disabling TCG. *_ppc_opcodes were created to make cpu_init.c have a few less ifdefs, since they are not needed. softmmu_resize_hpt_* have to be created because the compiler can't automatically know they aren't used, but they should never be reached. Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br> Message-Id: <20210525115355.8254-4-bruno.larsen@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03target/ppc: added ifdefs around TCG-only codeBruno Larsen (billionai)4-6/+44
excp_helper.c, mmu-hash64.c and mmu_helper.c have some function declarations that are TCG-only, and couldn't be easily moved to a TCG only file, so ifdefs were added around them. We also needed ifdefs around some header files because helper-proto.h includes trace/generated-helpers.h, which is never created when building without TCG, and cpu_ldst.h includes tcg/tcg.h, whose containing folder is not included as a -iquote. As future cleanup, we could change the part of the configuration script to add those. cpu_init.c also had a callback definition that is TCG only and could be removed as part of a future cleanup (all the dump_statistics part is almost never used and will become obsolete as we transition to using decodetree). Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br> Message-Id: <20210525115355.8254-3-bruno.larsen@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03target/ppc: used ternary operator when registering MASBruno Larsen (billionai)1-6/+3
The write calback decision when registering the MAS SPR has been turned into a ternary operation, rather than an if-then-else block. This was done because when building without TCG, even though the compiler will optimize away the pointers to spr_write_generic*, it doesn't optimize away the decision and assignment to the local pointer, creating compiler errors. This cleanup looked better than using ifdefs, so we decided to with it. Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210525115355.8254-2-bruno.larsen@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03spapr: Set LPCR to current AIL mode when starting a new CPUNicholas Piggin1-5/+9
TCG does not keep track of AIL mode in a central place, it's based on the current LPCR[AIL] bits. Synchronize the new CPU's LPCR to the current LPCR in rtas_start_cpu(), similarly to the way the ILE bit is synchronized. Open-code the ILE setting as well now that the caller's LPCR is available directly, there is no need for the indirection. Without this, under both TCG and KVM, adding a POWER8/9/10 class CPU with a new core ID after a modern Linux has booted results in the new CPU's LPCR missing the LPCR[AIL]=0b11 setting that the other CPUs have. This can cause crashes and unexpected behaviour. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-Id: <20210526091626.3388262-3-npiggin@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03spapr: Remove stale comment about power-saving LPCR bitsNicholas Piggin1-1/+0
Commit 47a9b551547 ("spapr: Clean up handling of LPCR power-saving exit bits") moved this logic but did not remove the comment from the previous location. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-Id: <20210526091626.3388262-2-npiggin@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03target/ppc: fold ppc_store_ptcr into it's only callerBruno Larsen (billionai)3-30/+23
ppc_store_ptcr, defined in mmu_helper.c, was only used by helper_store_ptcr, in misc_helper.c. To avoid possible confusion, the function was folded into the helper. Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br> Message-Id: <20210526143516.125582-1-bruno.larsen@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03spapr: nvdimm: Fix the persistent-memory root node name in device treeShivaprasad G Bhat1-2/+2
The FDT code is adding the pmem root node by name "persistent-memory" which should have been "ibm,persistent-memory". The linux fetches the device tree nodes by type and it has been working correctly as the type is correct. If someone searches by its intended name it would fail, so fix that. Reported-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com> Signed-off-by: Shivaprasad G Bhat <sbhat@linux.ibm.com> Message-Id: <162204278956.219.9061511386011411578.stgit@cc493db1e665> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03spapr: nvdimm: Forward declare and move the definitionsShivaprasad G Bhat2-12/+14
The subsequent patches add definitions which tend to get the compilation to cyclic dependency. So, prepare with forward declarations, move the definitions and clean up. Signed-off-by: Shivaprasad G Bhat <sbhat@linux.ibm.com> Message-Id: <162133925415.610.11584121797866216417.stgit@4f1e6f2bd33e> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03spapr: Fix EEH capability issue on KVM guest for PCI passthruMahesh Salgaonkar1-7/+33
With upstream kernel, especially after commit 98ba956f6a389 ("powerpc/pseries/eeh: Rework device EEH PE determination") we see that KVM guest isn't able to enable EEH option for PCI pass-through devices anymore. [root@atest-guest ~]# dmesg | grep EEH [ 0.032337] EEH: pSeries platform initialized [ 0.298207] EEH: No capable adapters found: recovery disabled. [root@atest-guest ~]# So far the linux kernel was assuming pe_config_addr equal to device's config_addr and using it to enable EEH on the PE through ibm,set-eeh-option RTAS call. Which wasn't the correct way as per PAPR. The linux kernel commit 98ba956f6a389 fixed this flow. With that fixed, linux now uses PE config address returned by ibm,get-config-addr-info2 RTAS call to enable EEH option per-PE basis instead of per-device basis. However this has uncovered a bug in qemu where ibm,set-eeh-option is treating PE config address as per-device config address. Hence in qemu guest with recent kernel the ibm,set-eeh-option RTAS call fails with -3 return value indicating that there is no PCI device exist for the specified PE config address. The rtas_ibm_set_eeh_option call uses pci_find_device() to get the PC device that matches specific bus and devfn extracted from PE config address passed as argument. Thus it tries to map the PE config address to a single specific PCI device 'bus->devices[devfn]' which always results into checking device on slot 0 'bus->devices[0]'. This succeeds when there is a pass-through device (vfio-pci) present on slot 0. But in cases where there is no pass-through device present in slot 0, but present in non-zero slots, ibm,set-eeh-option call fails to enable the EEH capability. hw/ppc/spapr_pci_vfio.c: spapr_phb_vfio_eeh_set_option() case RTAS_EEH_ENABLE: { PCIHostState *phb; PCIDevice *pdev; /* * The EEH functionality is enabled on basis of PCI device, * instead of PE. We need check the validity of the PCI * device address. */ phb = PCI_HOST_BRIDGE(sphb); pdev = pci_find_device(phb->bus, (addr >> 16) & 0xFF, (addr >> 8) & 0xFF); if (!pdev || !object_dynamic_cast(OBJECT(pdev), "vfio-pci")) { return RTAS_OUT_PARAM_ERROR; } hw/pci/pci.c:pci_find_device() PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn) { bus = pci_find_bus_nr(bus, bus_num); if (!bus) return NULL; return bus->devices[devfn]; } This patch fixes ibm,set-eeh-option to check for presence of any PCI device (vfio-pci) under specified bus and enable the EEH if found. The current code already makes sure that all the devices on that bus are from same iommu group (within same PE) and fail very early if it does not. After this fix guest is able to find EEH capable devices and enable EEH recovery on it. [root@atest-guest ~]# dmesg | grep EEH [ 0.048139] EEH: pSeries platform initialized [ 0.405115] EEH: Capable adapter found: recovery enabled. [root@atest-guest ~]# Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Mahesh Salgaonkar <mahesh@linux.ibm.com> Message-Id: <162158429107.145117.5843504911924013125.stgit@jupiter> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03spapr: Don't hijack current_machine->boot_orderGreg Kurz2-3/+8
QEMU 6.0 moved all the -boot variables to the machine. Especially, the removal of the boot_order static changed the handling of '-boot once' from: if (boot_once) { qemu_boot_set(boot_once, &error_fatal); qemu_register_reset(restore_boot_order, g_strdup(boot_order)); } to if (current_machine->boot_once) { qemu_boot_set(current_machine->boot_once, &error_fatal); qemu_register_reset(restore_boot_order, g_strdup(current_machine->boot_order)); } This means that we now register as subsequent boot order a copy of current_machine->boot_once that was just set with the previous call to qemu_boot_set(), i.e. we never transition away from the once boot order. It is certainly fragile^Wwrong for the spapr code to hijack a field of the base machine type object like that. The boot order rework simply turned this software boundary violation into an actual bug. Have the spapr code to handle that with its own field in SpaprMachineState. Also kfree() the initial boot device string when "once" was used. Fixes: 4b7acd2ac821 ("vl: clean up -boot variables") Resolves: https://bugzilla.redhat.com/show_bug.cgi?id=1960119 Cc: pbonzini@redhat.com Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <20210521160735.1901914-1-groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03target/ppc: removed unnecessary inclusion of helper-proto.hBruno Larsen (billionai)4-4/+0
These files included helper-proto.h, but didn't use or declare any helpers, so the #include has been removed Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210521201759.85475-6-bruno.larsen@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03target/ppc: reduce usage of fpscr_set_rounding_modeBruno Larsen (billionai)1-3/+5
It is preferable to store the current rounding mode and retore from that than recalculating from fpscr, so we changed the behavior of do_fri and VSX_ROUND to do it like that. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210521201759.85475-4-bruno.larsen@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03target/ppc: moved ppc_store_lpcr and ppc_store_msr to cpu.cBruno Larsen (billionai)2-16/+17
These functions are used in hw/ppc logic, during machine startup, which means it must be compiled when --disable-tcg is selected, and so it has been moved into a common code file Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20210521201759.85475-3-bruno.larsen@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03target/ppc: cleaned error_report from ppc_store_sdr1Bruno Larsen (billionai)1-4/+4
Changed how the function ppc_store_sdr1, from error_report(...) to qemu_log_mask(LOG_GUEST_ERROR, ...). Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br> Suggested-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210521201759.85475-2-bruno.larsen@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-02Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into stagingPeter Maydell24-138/+241
Block layer patches - NBD server: Fix crashes related to switching between AioContexts - file-posix: Workaround for discard/write_zeroes on buggy filesystems - Follow-up fixes for the reopen vs. permission changes - quorum: Fix error handling for flush - block-copy: Refactor copy_range handling - docs: Describe how to use 'null-co' block driver # gpg: Signature made Wed 02 Jun 2021 14:44:15 BST # gpg: using RSA key DC3DEB159A9AF95D3D7456FE7F09B272C88F2FD6 # gpg: issuer "kwolf@redhat.com" # gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" [full] # Primary key fingerprint: DC3D EB15 9A9A F95D 3D74 56FE 7F09 B272 C88F 2FD6 * remotes/kevin/tags/for-upstream: docs/secure-coding-practices: Describe how to use 'null-co' block driver block-copy: refactor copy_range handling block-copy: fix block_copy_task_entry() progress update nbd/server: Use drained block ops to quiesce the server block-backend: add drained_poll block: improve permission conflict error message block: simplify bdrv_child_user_desc() block/vvfat: inherit child_vvfat_qcow from child_of_bds block: improve bdrv_child_get_parent_desc() block-backend: improve blk_root_get_parent_desc() block: document child argument of bdrv_attach_child_common() block/file-posix: Try other fallbacks after invalid FALLOC_FL_ZERO_RANGE block/file-posix: Fix problem with fallocate(PUNCH_HOLE) on GPFS block: drop BlockBackendRootState::read_only block: drop BlockDriverState::read_only block: consistently use bdrv_is_read_only() block/vvfat: fix vvfat_child_perm crash block/vvfat: child_vvfat_qcow: add .get_parent_aio_context, fix crash qemu-io-cmds: assert that we don't have .perm requested in no-blk case block/quorum: Provide .bdrv_co_flush instead of .bdrv_co_flush_to_disk Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-02Merge remote-tracking branch ↵Peter Maydell97-591/+141
'remotes/thuth-gitlab/tags/pull-request-2021-06-02' into staging * Update the references to some doc files (use *.rst instead of *.txt) * Bump minimum versions of some requirements after removing CentOS 7 support # gpg: Signature made Wed 02 Jun 2021 08:12:18 BST # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * remotes/thuth-gitlab/tags/pull-request-2021-06-02: configure: bump min required CLang to 6.0 / XCode 10.0 configure: bump min required GCC to 7.5.0 configure: bump min required glib version to 2.56 tests/docker: drop CentOS 7 container tests/vm: convert centos VM recipe to CentOS 8 crypto: drop used conditional check crypto: bump min gnutls to 3.5.18, dropping RHEL-7 support crypto: bump min gcrypt to 1.8.0, dropping RHEL-7 support crypto: drop back compatibility typedefs for nettle crypto: bump min nettle to 3.4, dropping RHEL-7 support patchew: move quick build job from CentOS 7 to CentOS 8 container block/ssh: Bump minimum libssh version to 0.8.7 docs: fix references to docs/devel/s390-dasd-ipl.rst docs: fix references to docs/specs/tpm.rst docs: fix references to docs/devel/build-system.rst docs: fix references to docs/devel/atomics.rst docs: fix references to docs/devel/tracing.rst Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.1 at 2025-01-28 15:08:01 +0000