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2023-09-07configure, meson: remove target OS symbols from config-host.makPaolo Bonzini12-50/+49
Stop applying config-host.mak to the sourcesets, since it does not have any more CONFIG_* symbols coming from the command line. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-09-07configure, meson: remove CONFIG_SOLARIS from config-host.makPaolo Bonzini3-11/+11
CONFIG_SOLARIS is only used to pick tap implementations. But the target OS is invariant and does not depend on the configuration, so move away from config_host and just use unconditional rules in softmmu_ss. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-09-07configure, meson: move --enable-plugins to mesonPaolo Bonzini8-18/+23
While the option still needs to be parsed in the configure script (it's needed by tests/tcg, and also to decide about recursing into contrib/plugins), passing it to Meson can be done with -D instead of using config-host.mak. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-09-07configure: unify recursion into sub-MakefilesPaolo Bonzini2-20/+20
Treat contrib/plugins the same as the firmware. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-09-07contrib/plugins: use an independent makefilePaolo Bonzini2-11/+20
The initial reason to write this patch was to remove the last use of CONFIG_DEBUG_TCG from the makefiles; the flags to use to build TCG plugins are unrelated to --enable-debug-tcg, and instead they should be the same as those used to build emulators (the plugins are not build via meson for demonstration reasons only). However, since contrib/plugins/Makefile is also the last case of doing a compilation job using config-host.mak, go a step further and make it use a completely separate configuration file, removing all references to compilers from the toplevel config-host.mak. Clean up references to empty variables, and use .SECONDARY so that intermediate object files are not deleted. Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-09-07configure: move --enable-debug-tcg to mesonPaolo Bonzini4-11/+8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-09-07configure: remove boolean variables for targetsPaolo Bonzini1-42/+13
Just use $targetos always. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-09-07meson: compile bundled device treesPaolo Bonzini2-23/+21
If dtc is available, compile the .dts files in the pc-bios directory instead of using the precompiled binaries. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-09-07configure: create native file with contents of $host_ccPaolo Bonzini1-4/+11
The argument of --host-cc is not obeyed when cross compiling. To avoid this issue, place it in a configuration file and pass it to meson with --native-file. While at it, clarify that --host-cc is not obeyed anyway when _not_ cross compiling, because cc="$host_cc" is placed before --host-cc is processed. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-09-07configure: remove HOST_CCPaolo Bonzini2-2/+1
$(HOST_CC) is only used to invoke the preprocessor, and $(CC) can be used instead now that there is a Tricore C compiler. Remove the variable from config-host.mak. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-09-07meson: update unsupported host/CPU messagesPaolo Bonzini1-19/+26
Unsupported CPU and OSes are not really going away, but the project simply does not guarantee that they work. Rephrase the messages accordingly. While at it, move the warning for TCI performance at the end where it is more visible. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-09-07meson: do not unnecessarily use cmake for dependenciesPaolo Bonzini2-2/+2
Both gvnc and sysprof-capture come with pkg-config files, so specify the method to find them. Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-09-07contrib/plugins: add Darwin supportPaolo Bonzini1-0/+4
Under Darwin, using -shared makes it impossible to have undefined symbols and -bundle has to be used instead; so detect the OS and use different options. Based-on: <20230907101811.469236-1-pbonzini@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-09-07contrib/plugins/lockstep: Fix string formatPhilippe Mathieu-Daudé1-3/+8
This fixes on Darwin: plugins/lockstep.c:138:25: warning: format specifies type 'unsigned long' but the argument has type 'uint64_t' (aka 'unsigned long long') [-Wformat] us->pc, them->pc, g_slist_length(divergence_log), ^~~~~~ plugins/lockstep.c:138:33: warning: format specifies type 'unsigned long' but the argument has type 'uint64_t' (aka 'unsigned long long') [-Wformat] us->pc, them->pc, g_slist_length(divergence_log), ^~~~~~~~ plugins/lockstep.c:148:25: warning: format specifies type 'unsigned long' but the argument has type 'uint64_t' (aka 'unsigned long long') [-Wformat] us->pc, us->insn_count, them->pc, them->insn_count); ^~~~~~ plugins/lockstep.c:148:49: warning: format specifies type 'unsigned long' but the argument has type 'uint64_t' (aka 'unsigned long long') [-Wformat] us->pc, us->insn_count, them->pc, them->insn_count); ^~~~~~~~ plugins/lockstep.c:156:36: warning: format specifies type 'unsigned long' but the argument has type 'uint64_t' (aka 'unsigned long long') [-Wformat] prev->block->pc, prev->block->insns, ^~~~~~~~~~~~~~~ plugins/lockstep.c:156:53: warning: format specifies type 'long' but the argument has type 'uint64_t' (aka 'unsigned long long') [-Wformat] prev->block->pc, prev->block->insns, ^~~~~~~~~~~~~~~~~~ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230907105004.88600-5-philmd@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-09-07contrib/plugins/howvec: Fix string formatPhilippe Mathieu-Daudé1-2/+4
This fixes on Darwin: plugins/howvec.c:186:40: warning: format specifies type 'long' but the argument has type 'uint64_t' (aka 'unsigned long long') [-Wformat] class->count); ^~~~~~~~~~~~ plugins/howvec.c:213:36: warning: format specifies type 'long' but the argument has type 'uint64_t' (aka 'unsigned long long') [-Wformat] rec->count, ^~~~~~~~~~ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230907105004.88600-4-philmd@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-09-07contrib/plugins/drcov: Fix string formatPhilippe Mathieu-Daudé1-1/+1
This fixes on Darwin: plugins/drcov.c:52:13: warning: format specifies type 'unsigned long' but the argument has type 'uint64_t' (aka 'unsigned long long') [-Wformat] start_code, end_code, entry, path); ^~~~~~~~~~ plugins/drcov.c:52:25: warning: format specifies type 'unsigned long' but the argument has type 'uint64_t' (aka 'unsigned long long') [-Wformat] start_code, end_code, entry, path); ^~~~~~~~ plugins/drcov.c:52:35: warning: format specifies type 'unsigned long' but the argument has type 'uint64_t' (aka 'unsigned long long') [-Wformat] start_code, end_code, entry, path); ^~~~~ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230907105004.88600-3-philmd@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-09-07contrib/plugins/cache: Fix string formatPhilippe Mathieu-Daudé1-9/+10
This fixes on Darwin: plugins/cache.c:550:28: warning: format specifies type 'unsigned long' but the argument has type 'uint64_t' (aka 'unsigned long long') [-Wformat] l1_daccess, ^~~~~~~~~~ plugins/cache.c:551:28: warning: format specifies type 'unsigned long' but the argument has type 'uint64_t' (aka 'unsigned long long') [-Wformat] l1_dmisses, ^~~~~~~~~~ plugins/cache.c:553:28: warning: format specifies type 'unsigned long' but the argument has type 'uint64_t' (aka 'unsigned long long') [-Wformat] l1_iaccess, ^~~~~~~~~~ plugins/cache.c:554:28: warning: format specifies type 'unsigned long' but the argument has type 'uint64_t' (aka 'unsigned long long') [-Wformat] l1_imisses, ^~~~~~~~~~ plugins/cache.c:560:32: warning: format specifies type 'unsigned long' but the argument has type 'uint64_t' (aka 'unsigned long long') [-Wformat] l2_access, ^~~~~~~~~ plugins/cache.c:561:32: warning: format specifies type 'unsigned long' but the argument has type 'uint64_t' (aka 'unsigned long long') [-Wformat] l2_misses, ^~~~~~~~~ plugins/cache.c:665:52: warning: format specifies type 'long' but the argument has type 'uint64_t' (aka 'unsigned long long') [-Wformat] g_string_append_printf(rep, ", %ld, %s\n", insn->l1_dmisses, ~~~ ^~~~~~~~~~~~~~~~ %llu plugins/cache.c:678:52: warning: format specifies type 'long' but the argument has type 'uint64_t' (aka 'unsigned long long') [-Wformat] g_string_append_printf(rep, ", %ld, %s\n", insn->l1_imisses, ~~~ ^~~~~~~~~~~~~~~~ %llu plugins/cache.c:695:52: warning: format specifies type 'long' but the argument has type 'uint64_t' (aka 'unsigned long long') [-Wformat] g_string_append_printf(rep, ", %ld, %s\n", insn->l2_misses, ~~~ ^~~~~~~~~~~~~~~ %llu Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230907105004.88600-2-philmd@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-09-07contrib/plugins: remove -soname argumentPaolo Bonzini1-1/+1
-soname is not needed for runtime-loaded modules. For example, Meson says: if not isinstance(target, build.SharedModule) or target.force_soname: # Add -Wl,-soname arguments on Linux, -install_name on OS X commands += linker.get_soname_args( self.environment, target.prefix, target.name, target.suffix, target.soversion, target.darwin_versions) (force_soname is set is shared modules are linked into a build target, which is not the case here. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-09-01util/async-teardown.c: move to softmmu/, only build it when system build is ↵Michael Tokarev3-1/+1
requested Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Eric Blake <eblake@redhat.com> Message-ID: <20230901101302.3618955-9-mjt@tls.msk.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-09-01softmmu/vl.c: inline include/qemu/qemu-options.h into vl.cMichael Tokarev2-42/+10
qemu-options.h just includes qemu-options.def with some #defines. We already do this in vl.c in other place. Since no other file includes qemu-options.h anymore, just inline it in vl.c. This effectively reverts second half of commit 59a5264b99434. Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Eric Blake <eblake@redhat.com> Message-ID: <20230901101302.3618955-8-mjt@tls.msk.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-09-01os-posix.c: remove unneeded #includesMichael Tokarev1-2/+0
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Eric Blake <eblake@redhat.com> Message-ID: <20230901101302.3618955-7-mjt@tls.msk.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-09-01os-posix.c: move code aroundMichael Tokarev1-22/+27
this moves code blocks so that functions and variables which belongs to the same concept are now close to each other. There's no actual code changes in there. Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Eric Blake <eblake@redhat.com> Message-ID: <20230901101302.3618955-6-mjt@tls.msk.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-09-01os-posix.c, softmmu/vl.c: move os_parse_cmd_args() into qemu_init()Michael Tokarev4-87/+73
This will stop linking softmmu-specific os_parse_cmd_args() into every qemu executable which happens to use other functions from os-posix.c, such as os_set_line_buffering() or os_setup_signal_handling(). Also, since there's no win32-specific options, *all* option parsing is now done in softmmu/vl.c:qemu_init(), which is easier to read without extra indirection, - all options are in the single function now. This effectively reverts commit 59a5264b99434. Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Eric Blake <eblake@redhat.com> Message-ID: <20230901101302.3618955-5-mjt@tls.msk.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-09-01os-posix.c: create and export os_set_chroot()Michael Tokarev2-2/+8
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Eric Blake <eblake@redhat.com> Message-ID: <20230901101302.3618955-4-mjt@tls.msk.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-09-01os-posix.c: create and export os_set_runas()Michael Tokarev2-7/+17
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20230901101302.3618955-3-mjt@tls.msk.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-09-01include/sysemu/os-posix.h: move *daemonize* declarations togetherMichael Tokarev1-3/+2
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Eric Blake <eblake@redhat.com> Message-ID: <20230901101302.3618955-2-mjt@tls.msk.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-09-01target/i386: Add support for AMX-COMPLEX in CPUID enumerationTao Su2-1/+3
Latest Intel platform GraniteRapids-D introduces AMX-COMPLEX, which adds two instructions to perform matrix multiplication of two tiles containing complex elements and accumulate the results into a packed single precision tile. AMX-COMPLEX is enumerated via CPUID.(EAX=7,ECX=1):EDX[bit 8]. Add the CPUID definition for AMX-COMPLEX, AMX-COMPLEX will be enabled automatically when using '-cpu host' and KVM advertises AMX-COMPLEX to userspace. Signed-off-by: Tao Su <tao1.su@linux.intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Message-ID: <20230830074324.84059-1-tao1.su@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-09-01target/i386: fix memory operand size for CVTPS2PDPaolo Bonzini2-7/+37
CVTPS2PD only loads a half-register for memory, unlike the other operations under 0x0F 0x5A. "Unpack" the group into separate emission functions instead of using gen_unary_fp_sse. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-09-01target/i386: generalize operand size "ph" for use in CVTPS2PDPaolo Bonzini2-4/+4
CVTPS2PD only loads a half-register for memory, like CVTPH2PS. It can reuse the "ph" packed half-precision size to load a half-register, but rename it to "xh" because it is now a variation of "x" (it is not used only for half-precision values). Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-09-01target/i386: raise FERR interrupt with iothread lockedPaolo Bonzini2-1/+13
Otherwise tcg_handle_interrupt() triggers an assertion failure: #5 0x0000555555c97369 in tcg_handle_interrupt (cpu=0x555557434cb0, mask=2) at ../accel/tcg/tcg-accel-ops.c:83 #6 tcg_handle_interrupt (cpu=0x555557434cb0, mask=2) at ../accel/tcg/tcg-accel-ops.c:81 #7 0x0000555555b4d58b in pic_irq_request (opaque=<optimized out>, irq=<optimized out>, level=1) at ../hw/i386/x86.c:555 #8 0x0000555555b4f218 in gsi_handler (opaque=0x5555579423d0, n=13, level=1) at ../hw/i386/x86.c:611 #9 0x00007fffa42bde14 in code_gen_buffer () #10 0x0000555555c724bb in cpu_tb_exec (cpu=cpu@entry=0x555557434cb0, itb=<optimized out>, tb_exit=tb_exit@entry=0x7fffe9bfd658) at ../accel/tcg/cpu-exec.c:457 Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1808 Reported-by: NyanCatTW1 <https://gitlab.com/a0939712328> Co-developed-by: Richard Henderson <richard.henderson@linaro.org>' Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-09-01linux-user, bsd-user: disable on unsupported host architecturesPaolo Bonzini1-17/+23
Safe signal handling around system calls is mandatory for user-mode emulation, and requires a small piece of handwritten assembly code. So refuse to compile unless the common-user/host subdirectory exists for the host architecture that was detected or selected with --cpu. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-08-31Merge tag 'quick-fix-pull-request' of https://gitlab.com/bsdimp/qemu into ↵Stefan Hajnoczi2-30/+27
staging Pull request: fix ci by fixing clang-user # -----BEGIN PGP SIGNATURE----- # Comment: GPGTools - https://gpgtools.org # # iQIzBAABCgAdFiEEIDX4lLAKo898zeG3bBzRKH2wEQAFAmTvYpcACgkQbBzRKH2w # EQCKvhAA3nfvm+UMoRbOjFGuOOZKy+HR+nk40rxHa8CzOabbJnx4EtdBZTnNJ+f5 # WxLvEIzQw6iLYoqr6Rkcn0MkfYryesDScig7tQW0A87DtivXbDyrRbcmAQuCrcSe # EpEqjBOueiC9xe1U9hzdpNyBkuXQWFUNGKX6swR5vpOEb1hHKzFMY+60vEgcjcjQ # /y7cQcwRJeMNyBEwAM4HSgcVIKxB8ZmIQpIbsWJPAJhEZZE6SvTiKhM0PlZvrwnv # dlEV8F68f3cBka0QmX5JJNJQdXn+2gb2Ix06dm8z7BWtiZoH/rcJ0FfVjMk7bkcC # 2e0J0jI9JTf1MKNGHbO8V2YoZw+jCB9nr6N8HEymgla7bK6QPD6LIdTs0i6PUEB8 # PUf902NrOS+kbWTGsb9GINegklk3pJ0jnFZagqfCUxARQ2qrqmA6q5vg9d0FjPVl # vJ13weKkSHW126/4Wr23EhUFIoYtiuMjgz/Bjd5TvzhvnVGJiPJaY9sGpgZZ3PJJ # EPCRms5MRut/NE0znKQ9ozAz1FMdVd2XnXeClWJd2NUmGc7ZbBGMcSvUYdC9KLIK # oSQRBTUDgGIdHnB+g367vKs98ir+03gOcpQk9z0fy25wCymmp/Uco8jsm6hCgSGn # x7b9R6/+92xd/IZFZm5N3/llu6JHYPEMhdg8evNp9VTFPoi9PYc= # =jG8p # -----END PGP SIGNATURE----- # gpg: Signature made Wed 30 Aug 2023 11:39:03 EDT # gpg: using RSA key 2035F894B00AA3CF7CCDE1B76C1CD1287DB01100 # gpg: Good signature from "Warner Losh <wlosh@netflix.com>" [unknown] # gpg: aka "Warner Losh <imp@bsdimp.com>" [unknown] # gpg: aka "Warner Losh <imp@freebsd.org>" [unknown] # gpg: aka "Warner Losh <imp@village.org>" [unknown] # gpg: aka "Warner Losh <wlosh@bsdimp.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 2035 F894 B00A A3CF 7CCD E1B7 6C1C D128 7DB0 1100 * tag 'quick-fix-pull-request' of https://gitlab.com/bsdimp/qemu: bsd-user: Move PRAGMA_DISABLE_PACKED_WARNING etc to qemu.h Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-08-31Merge tag 'pull-target-arm-20230831' of ↵Stefan Hajnoczi31-358/+1379
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * Some of the preliminary patches for Cortex-A710 support * i.MX7 and i.MX6UL refactoring * Implement SRC device for i.MX7 * Catch illegal-exception-return from EL3 with bad NSE/NS * Use 64-bit offsets for holding time_t differences in RTC devices * Model correct number of MPU regions for an505, an521, an524 boards # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmTwbukZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3ihBD/wK8Iz0KpTAwZBDAodnSZrh # tQnJAvYFp8CxA4O8sZ9IeWsZh90gzsTCZi0NqUTTzvWCJfxkB7qTPdlJT5IzVxou # oEUk2aogSJhRA3XRJzqArXsPlnZGSYDbtwKx4VtfCvOCCH08Y7nhnFaRj1oFnR4Q # 0PE/8YtGXTBxLHrO8U3tomg7zElzOUP8ZVZtb30BOyw1jtfSD03IZR8dzpA43u1E # Hh418WvVekmwFoFNh8yUeHzbyXMZufzvbJPuDGJ8pPWwIpvSG6chOnKF8jZll+Ur # DqOsDkGlQgcBR2QwYfSPClrEkX8yahJ95PBfM6giG+DQC7OiElqXqTiUGZcpgUVo # uSUbzS4YPsxCnyVV6SBXV+f/8hdXBxOSHTgl7OAFa8X9OwWwspxHJ/v2o/2ibnUT # hTTkFp/w1nQwVEN8xf1DOUpm/J2Wr8UeH4f776daSrfKAol2BKbHb8dOgGLQCwqb # G+iDcE4bkzRqly6f+uVk8xSEZDd9P1NYoxKV+gNlV1dTspdHVpTC+rXMa8dRw5hI # 4KgaAslj++Xa229xkjORXCJ1cICRIebYg7+SjvTtGBYsFV7plsCcYb/R9yLmhVCf # fKHKKaYe9sQJ82apOIkTc+nnW8BQQx6XUmU/A//iZ8JGLk6DpJcZ8f1m/2rVZTsl # 9+lsmpBf4w+uR4o+Womhfw== # =MFh3 # -----END PGP SIGNATURE----- # gpg: Signature made Thu 31 Aug 2023 06:43:53 EDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20230831' of https://git.linaro.org/people/pmaydell/qemu-arm: (24 commits) hw/arm: Set number of MPU regions correctly for an505, an521, an524 hw/arm/armv7m: Add mpu-ns-regions and mpu-s-regions properties target/arm: Do all "ARM_FEATURE_X implies Y" checks in post_init rtc: Use time_t for passing and returning time offsets hw/rtc/aspeed_rtc: Use 64-bit offset for holding time_t difference hw/rtc/twl92230: Use int64_t for sec_offset and alm_sec hw/rtc/m48t59: Use 64-bit arithmetic in set_alarm() target/arm: Catch illegal-exception-return from EL3 with bad NSE/NS Add i.MX7 SRC device implementation Add i.MX7 missing TZ devices and memory regions Refactor i.MX7 processor code Add i.MX6UL missing devices. Refactor i.MX6UL processor code Remove i.MX7 IOMUX GPR device from i.MX6UL target/arm: properly document FEAT_CRC32 target/arm: Implement FEAT_HPDS2 as a no-op target/arm: Suppress FEAT_TRBE (Trace Buffer Extension) target/arm: Apply access checks to neoverse-v1 special registers target/arm: Apply access checks to neoverse-n1 special registers target/arm: Introduce make_ccsidr64 ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-08-31Merge tag 'xen-virtio-2-tag' of https://gitlab.com/sstabellini/qemu into stagingStefan Hajnoczi2-0/+104
xen-virtio-2-tag # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEE0E4zq6UfZ7oH0wrqiU+PSHDhrpAFAmTv65wACgkQiU+PSHDh # rpC6vg/+II8XIOTccYdrUI61irTDznlY2gWzr4oYDmW7zThO1y7wfqBTVZvOhGnC # paPs7Xe2mJMHSci8Nx+S/jpOBGmGZ7vWxkYsLltlmEIjsdTpD1ZlGmCITNR80KG6 # edmARZ06MU21zRETXbMBmyglak+ph6BWHEOZWtokfZbGXl7oQ8kt1OvT6azuRvPF # r6woYIg4eADE2ykReGAuw4FOrRjtKSKjAOhGrEf2jT5yemaeYYv2fPeyGoq46jAw # +Ktn9luwkY+hgMSRm2CPrZ+nJPfDqQgfypClu5CpF0faIIvvogWW0lkJmeMKLYdM # yQgyUAmAFQMTjwo2yWQi3BJj+550gIM3i3By7AjX5Qs2+yILec7pAvD/d8XQh2KC # 47M/u8DMC+Cel/OHNW7eoO6jh4z0Yu6zgaa9rEusVAxZuDJpxc6kcopbrikXCgBr # yIaO8h8ryKJISFupu4Gi/Vs0WuDDL3z1q3kdhfqkBQ9wwyK9/McZM8ue9KObH1al # M/v5hsnnG+m/5ANH9BYpaCgjG51FGtzzgwlZGLVkCGEUMeNZ+mkROuu0krKfMeJA # qGQOOesGyOw7tjYvBvHG2JiFQhmXqExPydkhNw+Gi1lH1C1F08jJRXM45/YRhOm/ # KlMd+dVK5BG1Hk4vhDmppMJn5iEb0UVHCaV2bXQMBVOXIRqHJ2A= # =4KZ7 # -----END PGP SIGNATURE----- # gpg: Signature made Wed 30 Aug 2023 21:23:40 EDT # gpg: using RSA key D04E33ABA51F67BA07D30AEA894F8F4870E1AE90 # gpg: Good signature from "Stefano Stabellini <sstabellini@kernel.org>" [unknown] # gpg: aka "Stefano Stabellini <stefano.stabellini@eu.citrix.com>" [full] # Primary key fingerprint: D04E 33AB A51F 67BA 07D3 0AEA 894F 8F48 70E1 AE90 * tag 'xen-virtio-2-tag' of https://gitlab.com/sstabellini/qemu: xen_arm: Initialize RAM and add hi/low memory regions xen_arm: Create virtio-mmio devices during initialization Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-08-31Merge tag 'pull-maintainer-ominbus-300823-1' of ↵Stefan Hajnoczi30-295/+324
https://gitlab.com/stsquad/qemu into staging testing and gdbstub updates: - enable ccache for gitlab builds - fix various test info leakages for non V=1 - update style to allow loop vars - bump FreeBSD to v13.2 - clean-up gdbstub tests - various gdbstub doc and refactorings # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEEZoWumedRZ7yvyN81+9DbCVqeKkQFAmTvS2AACgkQ+9DbCVqe # KkRiRwgAhsinp2/KgnvkD0n6deQy/JWg9MfYIvvZacKEakIfQvCDoJ752AUZzUTw # ggQ+W2KuaoHTzwG+AOMLdzulkmspQ8xeFuD2aIpFjRMnZrO9jN2T4L0vcGLAd95c # 9QLqPeH8xRdhuK28+ILuYzKOKBcefQ44ufMLpxrS2iNITEsSg/Tw3MU91hbct49g # 3OR4bD1ueG5Ib/lXp8V/4GnRmfLdnp3k0i/6OHriq7Mpz4Lia67WblVsPEple66U # n7JCo2sI5/m+6p2tvKs7rH60xc8s1Za3kbK4ggEq3LVRfzVOordZqO+1ep6wklTY # 6nP9Ry9nZG3gqCmcNXfhoofm0vHaZA== # =Km9m # -----END PGP SIGNATURE----- # gpg: Signature made Wed 30 Aug 2023 10:00:00 EDT # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * tag 'pull-maintainer-ominbus-300823-1' of https://gitlab.com/stsquad/qemu: gdbstub: move comment for gdb_register_coprocessor gdbstub: replace global gdb_has_xml with a function gdbstub: refactor get_feature_xml gdbstub: remove unused user_ctx field gdbstub: fixes cases where wrong threads were reported to GDB on SIGINT tests/tcg: clean-up gdb confirm/pagination settings tests: remove test-gdbstub.py .gitlab-ci.d/cirrus.yml: Update FreeBSD to v13.2 docs/style: permit inline loop variables tests/tcg: remove quoting for info output tests/docker: cleanup non-verbose output gitlab: enable ccache for many build jobs Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-08-31hw/arm: Set number of MPU regions correctly for an505, an521, an524Peter Maydell3-0/+50
The IoTKit, SSE200 and SSE300 all default to 8 MPU regions. The MPS2/MPS3 FPGA images don't override these except in the case of AN547, which uses 16 MPU regions. Define properties on the ARMSSE object for the MPU regions (using the same names as the documented RTL configuration settings, and following the pattern we already have for this device of using all-caps names as the RTL does), and set them in the board code. We don't actually need to override the default except on AN547, but it's simpler code to have the board code set them always rather than tracking which board subtypes want to set them to a non-default value separately from what that value is. Tho overall effect is that for mps2-an505, mps2-an521 and mps3-an524 we now correctly use 8 MPU regions, while mps3-an547 stays at its current 16 regions. It's possible some guest code wrongly depended on the previous incorrectly modeled number of memory regions. (Such guest code should ideally check the number of regions via the MPU_TYPE register.) The old behaviour can be obtained with additional -global arguments to QEMU: For mps2-an521 and mps2-an524: -global sse-200.CPU0_MPU_NS=16 -global sse-200.CPU0_MPU_S=16 -global sse-200.CPU1_MPU_NS=16 -global sse-200.CPU1_MPU_S=16 For mps2-an505: -global sse-200.CPU0_MPU_NS=16 -global sse-200.CPU0_MPU_S=16 NB that the way the implementation allows this use of -global is slightly fragile: if the board code explicitly sets the properties on the sse-200 object, this overrides the -global command line option. So we rely on: - the boards that need fixing all happen to use the SSE defaults - we can write the board code to only set the property if it is different from the default, rather than having all boards explicitly set the property - the board that does need to use a non-default value happens to need to set it to the same value (16) we previously used This works, but there are some kinds of refactoring of the mps2-tz.c code that would break the support for -global here. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1772 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20230724174335.2150499-4-peter.maydell@linaro.org
2023-08-31hw/arm/armv7m: Add mpu-ns-regions and mpu-s-regions propertiesPeter Maydell2-0/+29
M-profile CPUs generally allow configuration of the number of MPU regions that they have. We don't currently model this, so our implementations of some of the board models provide CPUs with the wrong number of regions. RTOSes like Zephyr that hardcode the expected number of regions may therefore not run on the model if they are set up to run on real hardware. Add properties mpu-ns-regions and mpu-s-regions to the ARMV7M object, matching the ability of hardware to configure the number of Secure and NonSecure regions separately. Our actual CPU implementation doesn't currently support that, and it happens that none of the MPS boards we model set the number of regions differently for Secure vs NonSecure, so we provide an interface to the boards and SoCs that won't need to change if we ever do add that functionality in future, but make it an error to configure the two properties to different values. (The property name on the CPU is the somewhat misnamed-for-M-profile "pmsav7-dregion", so we don't follow that naming convention for the properties here. The TRM doesn't say what the CPU configuration variable names are, so we pick something, and follow the lowercase convention we already have for properties here.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20230724174335.2150499-3-peter.maydell@linaro.org
2023-08-31target/arm: Do all "ARM_FEATURE_X implies Y" checks in post_initPeter Maydell1-82/+97
Where architecturally one ARM_FEATURE_X flag implies another ARM_FEATURE_Y, we allow the CPU init function to only set X, and then set Y for it. Currently we do this in two places -- we set a few flags in arm_cpu_post_init() because we need them to decide which properties to create on the CPU object, and then we do the rest in arm_cpu_realizefn(). However, this is fragile, because it's easy to add a new property and not notice that this means that an X-implies-Y check now has to move from realize to post-init. As a specific example, the pmsav7-dregion property is conditional on ARM_FEATURE_PMSA && ARM_FEATURE_V7, which means it won't appear on the Cortex-M33 and -M55, because they set ARM_FEATURE_V8 and rely on V8-implies-V7, which doesn't happen until the realizefn. Move all of these X-implies-Y checks into a new function, which we call at the top of arm_cpu_post_init(), so the feature bits are available at that point. This does now give us the reverse issue, that if there's a feature bit which is enabled or disabled by the setting of a property then then X-implies-Y features that are dependent on that property need to be in realize, not in this new function. But the only one of those is the "EL3 implies VBAR" which is already in the right place, so putting things this way round seems better to me. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230724174335.2150499-2-peter.maydell@linaro.org
2023-08-31rtc: Use time_t for passing and returning time offsetsPeter Maydell2-4/+4
The functions qemu_get_timedate() and qemu_timedate_diff() take and return a time offset as an integer. Coverity points out that means that when an RTC device implementation holds an offset as a time_t, as the m48t59 does, the time_t will get truncated. (CID 1507157, 1517772). The functions work with time_t internally, so make them use that type in their APIs. Note that this won't help any Y2038 issues where either the device model itself is keeping the offset in a 32-bit integer, or where the hardware under emulation has Y2038 or other rollover problems. If we missed any cases of the former then hopefully Coverity will warn us about them since after this patch we'd be truncating a time_t in assignments from qemu_timedate_diff().) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-08-31hw/rtc/aspeed_rtc: Use 64-bit offset for holding time_t differencePeter Maydell2-4/+3
In the aspeed_rtc device we store a difference between two time_t values in an 'int'. This is not really correct when time_t could be 64 bits. Enlarge the field to 'int64_t'. This is a migration compatibility break for the aspeed boards. While we are changing the vmstate, remove the accidental duplicate of the offset field. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org>
2023-08-31hw/rtc/twl92230: Use int64_t for sec_offset and alm_secPeter Maydell1-2/+2
In the twl92230 device, use int64_t for the two state fields sec_offset and alm_sec, because we set these to values that are either time_t or differences between two time_t values. These fields aren't saved in vmstate anywhere, so we can safely widen them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-08-31hw/rtc/m48t59: Use 64-bit arithmetic in set_alarm()Peter Maydell1-1/+1
In the m48t59 device we almost always use 64-bit arithmetic when dealing with time_t deltas. The one exception is in set_alarm(), which currently uses a plain 'int' to hold the difference between two time_t values. Switch to int64_t instead to avoid any possible overflow issues. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-08-31target/arm: Catch illegal-exception-return from EL3 with bad NSE/NSPeter Maydell1-0/+9
The architecture requires (R_TYTWB) that an attempt to return from EL3 when SCR_EL3.{NSE,NS} are {1,0} is an illegal exception return. (This enforces that the CPU can't ever be executing below EL3 with the NSE,NS bits indicating an invalid security state.) We were missing this check; add it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230807150618.101357-1-peter.maydell@linaro.org
2023-08-31Add i.MX7 SRC device implementationJean-Christophe Dubois6-2/+356
The SRC device is normally used to start the secondary CPU. When running Linux directly, QEMU is emulating a PSCI interface that UBOOT is installing at boot time and therefore the fact that the SRC device is unimplemented is hidden as Qemu respond directly to PSCI requets without using the SRC device. But if you try to run a more bare metal application (maybe uboot itself), then it is not possible to start the secondary CPU as the SRC is an unimplemented device. This patch adds the ability to start the secondary CPU through the SRC device so that you can use this feature in bare metal applications. Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: ce9a0162defd2acee5dc7f8a674743de0cded569.1692964892.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-08-31Add i.MX7 missing TZ devices and memory regionsJean-Christophe Dubois2-0/+70
* Add TZASC as unimplemented device. - Allow bare metal application to access this (unimplemented) device * Add CSU as unimplemented device. - Allow bare metal application to access this (unimplemented) device * Add various memory segments - OCRAM - OCRAM EPDC - OCRAM PXP - OCRAM S - ROM - CAAM Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: f887a3483996ba06d40bd62ffdfb0ecf68621987.1692964892.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-08-31Refactor i.MX7 processor codeJean-Christophe Dubois2-123/+333
* Add Addr and size definition for all i.MX7 devices in i.MX7 header file. * Use those newly defined named constants whenever possible. * Standardize the way we init a familly of unimplemented devices - SAI - PWM - CAN * Add/rework few comments Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Message-id: 59e195d33e4d486a8d131392acd46633c8c10ed7.1692964892.git.jcd@tribudubois.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-08-31Add i.MX6UL missing devices.Jean-Christophe Dubois2-1/+17
* Add TZASC as unimplemented device. - Allow bare metal application to access this (unimplemented) device * Add CSU as unimplemented device. - Allow bare metal application to access this (unimplemented) device * Add 4 missing PWM devices Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 59e4dc56e14eccfefd379275ec19048dff9c10b3.1692964892.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-08-31Refactor i.MX6UL processor codeJean-Christophe Dubois2-60/+221
* Add Addr and size definition for most i.MX6UL devices in i.MX6UL header file. * Use those newly defined named constants whenever possible. * Standardize the way we init a familly of unimplemented devices - SAI - PWM - CAN * Add/rework few comments Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Message-id: d579043fbd4e4b490370783fda43fc02c8e9be75.1692964892.git.jcd@tribudubois.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-08-31Remove i.MX7 IOMUX GPR device from i.MX6ULJean-Christophe Dubois2-13/+0
i.MX7 IOMUX GPR device is not equivalent to i.MX6UL IOMUXC GPR device. In particular, register 22 is not present on i.MX6UL and this is actualy The only register that is really emulated in the i.MX7 IOMUX GPR device. Note: The i.MX6UL code is actually also implementing the IOMUX GPR device as an unimplemented device at the same bus adress and the 2 instantiations were actualy colliding. So we go back to the unimplemented device for now. Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Message-id: 48681bf51ee97646479bb261bee19abebbc8074e.1692964892.git.jcd@tribudubois.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-08-31target/arm: properly document FEAT_CRC32Alex Bennée2-1/+2
This is a mandatory feature for Armv8.1 architectures but we don't state the feature clearly in our emulation list. Also include FEAT_CRC32 comment in aarch64_max_tcg_initfn for ease of grepping. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20230824075406.1515566-1-alex.bennee@linaro.org Cc: qemu-stable@nongnu.org Message-Id: <20230222110104.3996971-1-alex.bennee@linaro.org> [PMM: pluralize 'instructions' in docs] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.1 at 2024-12-23 03:49:57 +0000