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2017-01-20s390x/pci: dynamically allocate iommuYi Min Zhao2-15/+64
When initializing a PCI device, an address space is required during PCI core initialization and before the call to the embedding object hotplug callback. To provide this AS, we allocate a S390PCIIOMMU object containing this AS. Initialization of S390PCIIOMMU object is done before the PCI device is completely created. So that we cannot associate the IOMMU with the device at the moment. To track the IOMMU object, we use g_hash functions with the PCI device's bus address as a key to provide an array of pointers indexed by the PCI device's devfn to the allocated IOMMU. Signed-off-by: Yi Min Zhao <zyimin@linux.vnet.ibm.com> Reviewed-by: Pierre Morel <pmorel@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2017-01-20s390x/pci: make S390PCIIOMMU inherit ObjectYi Min Zhao4-53/+71
Currently S390PCIIOMMU is a normal struct. Let's make it inherit Object in order to take advantage of QOM. In addition, we move some stuff related to IOMMU from S390PCIBusDevice to S390PCIIOMMU. Signed-off-by: Yi Min Zhao <zyimin@linux.vnet.ibm.com> Acked-by: Pierre Morel <pmorel@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2017-01-20s390x/kvm: use kvm_gsi_routing_enabled in flicFei Li1-2/+2
Let's use kvm_gsi_routing_enabled() to check if kvm supports KVM_CAP_IRQ_ROUTING in order to avoid a needless ioctl invocation. Signed-off-by: Fei Li <sherrylf@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2017-01-20s390x: add compat machine for 2.9Cornelia Huck1-1/+16
Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com>
2017-01-20s390x: remove double compat statementChristian Borntraeger1-2/+0
We chain our compat handler via the CCW_COMPAT macros and via the class_init function. (e.g. ccw_machine_2_7_class_options calls ccw_machine_2_8_class_options). As all class_init functions in that chain call SET_MACHINE_COMPAT for their compat settings, and SET_MACHINE_COMPAT will append there is no need to do that again. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2017-01-19Merge remote-tracking branch 'remotes/artyom/tags/pull-sun4v-20170118' into ↵Peter Maydell22-528/+1227
staging add OpenSPARC T1 emulation # gpg: Signature made Wed 18 Jan 2017 22:25:47 GMT # gpg: using RSA key 0x3360C3F7411A125F # gpg: Good signature from "Artyom Tarasenko <atar4qemu@gmail.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 2AD8 6149 17F4 B2D7 05C0 BB12 3360 C3F7 411A 125F * remotes/artyom/tags/pull-sun4v-20170118: (30 commits) target-sparc: fix up niagara machine target-sparc: move common cpu initialisation routines to sparc64.c target-sparc: implement sun4v RTC target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs target-sparc: store the UA2005 entries in sun4u format target-sparc: implement UA2005 ASI_MMU (0x21) target-sparc: add more registers to dump_mmu target-sparc: implement auto-demapping for UA2005 CPUs target-sparc: allow 256M sized pages target-sparc: simplify ultrasparc_tsb_pointer target-sparc: implement UA2005 TSB Pointers target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs target-sparc: replace the last tlb entry when no free entries left target-sparc: ignore writes to UA2005 CPU mondo queue register target-sparc: allow priveleged ASIs in hyperprivileged mode target-sparc: use direct address translation in hyperprivileged mode target-sparc: fix immediate UA2005 traps target-sparc: implement UA2005 rdhpstate and wrhpstate instructions target-sparc: implement UA2005 GL register target-sparc: implement UA2005 hypervisor traps ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-19Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20170117' into stagingPeter Maydell1-25/+20
tcg/i386 fixes # gpg: Signature made Tue 17 Jan 2017 22:58:04 GMT # gpg: using RSA key 0xAD1270CC4DD0279B # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>" # gpg: aka "Richard Henderson <rth@redhat.com>" # gpg: aka "Richard Henderson <rth@twiddle.net>" # Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC 16A4 AD12 70CC 4DD0 279B * remotes/rth/tags/pull-tcg-20170117: tcg/i386: Always use TZCNT when available Revert "tcg/i386: Rely on undefined/undocumented behaviour of BSF/BSR" Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-18target-sparc: fix up niagara machineArtyom Tarasenko6-39/+199
Remove the Niagara stub implementation from sun4u.c and add a machine, compatible with Legion simulator from the OpenSPARC T1 project. The machine uses the firmware supplied with the OpenSPARC T1 project, http://download.oracle.com/technetwork/systems/opensparc/OpenSPARCT1_Arch.1.5.tar.bz2 in the directory S10image/, and is able to boot the supplied Solaris 10 image. Note that for compatibility with the naming conventions for SPARC machines the new machine name is lowercase niagara. Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
2017-01-18target-sparc: move common cpu initialisation routines to sparc64.cArtyom Tarasenko5-345/+389
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
2017-01-18target-sparc: implement sun4v RTCArtyom Tarasenko4-0/+111
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-01-18target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUsArtyom Tarasenko1-0/+11
In OpenSPARC T1+ TWINX ASIs in store instructions are aliased with Block Initializing Store ASIs. "UltraSPARC T1 Supplement Draft D2.1, 14 May 2007" describes them in the chapter "5.9 Block Initializing Store ASIs" Integer stores of all sizes are allowed with these ASIs. Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-01-18target-sparc: store the UA2005 entries in sun4u formatArtyom Tarasenko2-8/+47
According to chapter 13.3 of the UltraSPARC T1 Supplement to the UltraSPARC Architecture 2005, only the sun4u format is available for data-access loads. Store UA2005 entries in the sun4u format to simplify processing. Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-01-18target-sparc: implement UA2005 ASI_MMU (0x21)Artyom Tarasenko1-0/+31
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-01-18target-sparc: add more registers to dump_mmuArtyom Tarasenko1-0/+2
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
2017-01-18target-sparc: implement auto-demapping for UA2005 CPUsArtyom Tarasenko1-0/+22
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-01-18target-sparc: allow 256M sized pagesArtyom Tarasenko1-17/+1
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-01-18target-sparc: simplify ultrasparc_tsb_pointerArtyom Tarasenko1-36/+15
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-01-18target-sparc: implement UA2005 TSB PointersArtyom Tarasenko2-22/+104
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-01-18target-sparc: use SparcV9MMU type for sparc64 I/D-MMUsArtyom Tarasenko4-37/+25
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-01-18target-sparc: replace the last tlb entry when no free entries leftArtyom Tarasenko1-2/+4
Implement the behavior described in the chapter 13.9.11 of UltraSPARC T1™ Supplement to the UltraSPARC Architecture 2005: "If a TLB Data-In replacement is attempted with all TLB entries locked and valid, the last TLB entry (entry 63) is replaced." Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-01-18target-sparc: ignore writes to UA2005 CPU mondo queue registerArtyom Tarasenko1-0/+1
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
2017-01-18target-sparc: allow priveleged ASIs in hyperprivileged modeArtyom Tarasenko1-14/+18
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-01-18target-sparc: use direct address translation in hyperprivileged modeArtyom Tarasenko2-5/+4
Please note that QEMU doesn't impelement Real->Physical address translation. The "Real Address" is always the "Physical Address". Suggested-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-01-18target-sparc: fix immediate UA2005 trapsArtyom Tarasenko1-1/+1
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-01-18target-sparc: implement UA2005 rdhpstate and wrhpstate instructionsArtyom Tarasenko1-2/+5
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
2017-01-18target-sparc: implement UA2005 GL registerArtyom Tarasenko6-7/+58
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-01-18target-sparc: implement UA2005 hypervisor trapsArtyom Tarasenko3-5/+39
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-01-18target-sparc: hypervisor mode takes over nucleus modeArtyom Tarasenko2-3/+7
Accordinf to UA2005, 9.3.3 "Address Space Identifiers", "In hyperprivileged mode, all instruction fetches and loads and stores with implicit ASIs use a physical address, regardless of the value of TL". Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-01-18target-sparc: implement UltraSPARC-T1 Strand status ASRArtyom Tarasenko1-0/+11
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
2017-01-18target-sparc: implement UA2005 scratchpad registersArtyom Tarasenko3-0/+26
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-01-18target-sparc: simplify replace_tlb_entry by using TTE_PGSIZEArtyom Tarasenko1-3/+2
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
2017-01-18target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor modeArtyom Tarasenko1-1/+2
As described in Chapter 5.7.6 of the UltraSPARC Architecture 2005, outstanding disrupting exceptions that are destined for privileged mode can only cause a trap when the virtual processor is in nonprivileged or privileged mode and PSTATE.ie = 1. At all other times, they are held pending. Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
2017-01-18target-sparc: add UltraSPARC T1 TLB #definesArtyom Tarasenko1-0/+4
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-01-18target-sparc: add UA2005 TTE bit #definesArtyom Tarasenko1-0/+17
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-01-18target-sparc: use explicit mmu register pointersArtyom Tarasenko2-12/+58
Use explicit register pointers while accessing D/I-MMU registers. Call cpu_unassigned_access on access to missing registers. Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
2017-01-18target-sparc: store cpu super- and hypervisor flags in TBArtyom Tarasenko2-5/+36
Suggested-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-01-18target-sparc: ignore MMU-faults if MMU is disabled in hypervisor modeArtyom Tarasenko2-2/+15
while IMMU/DMMU is disabled - ignore MMU-faults in hypervisorv mode or if CPU doesn't have hypervisor - signal TT_INSN_REAL_TRANSLATION_MISS/TT_DATA_REAL_TRANSLATION_MISS otherwise Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-01-17tcg/i386: Always use TZCNT when availableRichard Henderson1-3/+7
I think this is cleaner than sometimes using BSF. Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-17Revert "tcg/i386: Rely on undefined/undocumented behaviour of BSF/BSR"Richard Henderson1-22/+13
This reverts commit 4ac76910734209dab83ddd3795f08fc7889ef463. This fixes http://lists.nongnu.org/archive/html/qemu-devel/2017-01/msg03062.html While I think we could get away with relying on the undocumented behaviour, the tcg constraint system isn't powerful enough to properly describe the required (non-)overlap conditions. Reported-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-17Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' ↵Peter Maydell5-2/+46
into staging # gpg: Signature made Mon 16 Jan 2017 13:44:46 GMT # gpg: using RSA key 0x9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * remotes/stefanha/tags/tracing-pull-request: trace: Add event "guest_cpu_exit" trace: Fix dynamic event state on vCPU hot-unplug trace: Lock vCPU list when initializing dynamic tracing state trace-events: spelling fix Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-17Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2017-01-16' into ↵Peter Maydell297-5012/+4750
staging QAPI patches for 2017-01-16 # gpg: Signature made Mon 16 Jan 2017 09:26:49 GMT # gpg: using RSA key 0x3870B400EB918653 # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-qapi-2017-01-16: (180 commits) build-sys: add qapi doc generation targets build-sys: add txt documentation rules build-sys: use a generic TEXI2MAN rule build-sys: remove dvi doc generation build-sys: use --no-split for info docs: add qemu logo to pdf qapi: add qapi2texi script qmp-events: move 'MIGRATION_PASS' doc to schema qmp-events: move 'DUMP_COMPLETED' doc to schema qmp-events: move 'MEM_UNPLUG_ERROR' doc to schema qmp-events: move 'VSERPORT_CHANGE' doc to schema qmp-events: move 'QUORUM_REPORT_BAD' doc to schema qmp-events: move 'QUORUM_FAILURE' doc to schema qmp-events: move 'GUEST_PANICKED' doc to schema qmp-events: move 'BALLOON_CHANGE' doc to schema qmp-events: move 'ACPI_DEVICE_OST' doc to schema qmp-events: move 'MIGRATION' doc to schema qmp-events: move 'SPICE_MIGRATE_COMPLETED' doc to schema qmp-events: move 'SPICE_DISCONNECTED' doc to schema qmp-events: move 'SPICE_INITIALIZED' doc to schema ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-17Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into ↵Peter Maydell16-202/+1009
staging # gpg: Signature made Mon 16 Jan 2017 13:38:52 GMT # gpg: using RSA key 0x9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * remotes/stefanha/tags/block-pull-request: async: optimize aio_bh_poll aio: document locking aio-win32: remove walking_handlers, protecting AioHandler list with list_lock aio-posix: remove walking_handlers, protecting AioHandler list with list_lock aio: tweak walking in dispatch phase aio-posix: split aio_dispatch_handlers out of aio_dispatch qemu-thread: optimize QemuLockCnt with futexes on Linux aio: make ctx->list_lock a QemuLockCnt, subsuming ctx->walking_bh qemu-thread: introduce QemuLockCnt aio: rename bh_lock to list_lock block: get rid of bdrv_io_unplugged_begin/end Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-16Merge remote-tracking branch ↵Peter Maydell57-148/+151
'remotes/stsquad/tags/pull-tcg-common-tlb-reset-20170113-r1' into staging This is the same as the v3 posted except a re-base and a few extra signoffs # gpg: Signature made Fri 13 Jan 2017 14:26:46 GMT # gpg: using RSA key 0xFBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-tcg-common-tlb-reset-20170113-r1: cputlb: drop flush_global flag from tlb_flush cpu_common_reset: wrap TCG specific code in tcg_enabled() qom/cpu: move tlb_flush to cpu_common_reset Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-16trace: Add event "guest_cpu_exit"Lluís Vilanova2-0/+9
Signals the hot-unplugging of a virtual (guest) CPU. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Message-id: 148278748597.1404.10546320797997984932.stgit@fimbulvetr.bsc.es Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2017-01-16trace: Fix dynamic event state on vCPU hot-unplugLluís Vilanova3-0/+26
We need to disable per-vCPU events on a vCPU that is hot-unplugged to keep the dynamic event state global counters consistent. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Message-id: 148278748055.1404.1570530281528619895.stgit@fimbulvetr.bsc.es Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2017-01-16trace: Lock vCPU list when initializing dynamic tracing stateLluís Vilanova1-1/+10
Fixes potential corruption when a vCPU is hot-(un)plugged while initializing the current one. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Message-id: 148278747515.1404.6538173443841279200.stgit@fimbulvetr.bsc.es Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2017-01-16trace-events: spelling fixMarc-André Lureau1-1/+1
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-id: 20161212221759.28949-1-marcandre.lureau@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2017-01-16async: optimize aio_bh_pollPaolo Bonzini1-1/+9
Avoid entering the slow path of qemu_lockcnt_dec_and_lock if no bottom half has to be deleted. Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Fam Zheng <famz@redhat.com> Message-id: 20170112180800.21085-11-pbonzini@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2017-01-16aio: document lockingPaolo Bonzini2-24/+21
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Fam Zheng <famz@redhat.com> Message-id: 20170112180800.21085-10-pbonzini@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2017-01-16aio-win32: remove walking_handlers, protecting AioHandler list with list_lockPaolo Bonzini1-26/+47
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Fam Zheng <famz@redhat.com> Message-id: 20170112180800.21085-9-pbonzini@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
generated by cgit v1.1 at 2025-02-07 18:26:46 +0000