diff options
Diffstat (limited to 'tcg/tci.c')
| -rw-r--r-- | tcg/tci.c | 75 |
1 files changed, 21 insertions, 54 deletions
@@ -451,67 +451,70 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, *(uint32_t *)(t1 + t2) = t0; break; - /* Arithmetic operations (32 bit). */ + /* Arithmetic operations (mixed 32/64 bit). */ - case INDEX_op_add_i32: + CASE_32_64(add) t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 + t2); break; - case INDEX_op_sub_i32: + CASE_32_64(sub) t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 - t2); break; - case INDEX_op_mul_i32: + CASE_32_64(mul) t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 * t2); break; - case INDEX_op_div_i32: + CASE_32_64(and) t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); t2 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, (int32_t)t1 / (int32_t)t2); + tci_write_reg(regs, t0, t1 & t2); break; - case INDEX_op_divu_i32: + CASE_32_64(or) t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); t2 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint32_t)t1 / (uint32_t)t2); + tci_write_reg(regs, t0, t1 | t2); break; - case INDEX_op_rem_i32: + CASE_32_64(xor) t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); t2 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, (int32_t)t1 % (int32_t)t2); + tci_write_reg(regs, t0, t1 ^ t2); break; - case INDEX_op_remu_i32: + + /* Arithmetic operations (32 bit). */ + + case INDEX_op_div_i32: t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); t2 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint32_t)t1 % (uint32_t)t2); + tci_write_reg(regs, t0, (int32_t)t1 / (int32_t)t2); break; - case INDEX_op_and_i32: + case INDEX_op_divu_i32: t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); t2 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 & t2); + tci_write_reg(regs, t0, (uint32_t)t1 / (uint32_t)t2); break; - case INDEX_op_or_i32: + case INDEX_op_rem_i32: t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); t2 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 | t2); + tci_write_reg(regs, t0, (int32_t)t1 % (int32_t)t2); break; - case INDEX_op_xor_i32: + case INDEX_op_remu_i32: t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); t2 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 ^ t2); + tci_write_reg(regs, t0, (uint32_t)t1 % (uint32_t)t2); break; /* Shift/rotate operations (32 bit). */ @@ -695,24 +698,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, /* Arithmetic operations (64 bit). */ - case INDEX_op_add_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 + t2); - break; - case INDEX_op_sub_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 - t2); - break; - case INDEX_op_mul_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 * t2); - break; case INDEX_op_div_i64: t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); @@ -737,24 +722,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2); break; - case INDEX_op_and_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 & t2); - break; - case INDEX_op_or_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 | t2); - break; - case INDEX_op_xor_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 ^ t2); - break; /* Shift/rotate operations (64 bit). */ |