diff options
Diffstat (limited to 'target')
-rw-r--r-- | target/mips/cpu.h | 2 | ||||
-rw-r--r-- | target/mips/translate.c | 61 | ||||
-rw-r--r-- | target/mips/translate_init.inc.c | 40 |
3 files changed, 73 insertions, 30 deletions
diff --git a/target/mips/cpu.h b/target/mips/cpu.h index c4da7df..473d26d 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1173,7 +1173,7 @@ int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU bool cpu_supports_cps_smp(const char *cpu_type); -bool cpu_supports_isa(const char *cpu_type, unsigned int isa); +bool cpu_supports_isa(const char *cpu_type, uint64_t isa); void cpu_set_exception_base(int vp_index, target_ulong address); /* mips_int.c */ diff --git a/target/mips/translate.c b/target/mips/translate.c index ab307c4..e9b5d1d 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -3714,7 +3714,7 @@ static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt, } static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset, - uint32_t reg1, uint32_t reg2) + uint32_t reg1, uint32_t reg2, bool eva) { TCGv taddr = tcg_temp_local_new(); TCGv lladdr = tcg_temp_local_new(); @@ -3742,7 +3742,7 @@ static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset, tcg_gen_ld_i64(llval, cpu_env, offsetof(CPUMIPSState, llval_wp)); tcg_gen_atomic_cmpxchg_i64(val, taddr, llval, tval, - ctx->mem_idx, MO_64); + eva ? MIPS_HFLAG_UM : ctx->mem_idx, MO_64); if (reg1 != 0) { tcg_gen_movi_tl(cpu_gpr[reg1], 1); } @@ -18460,10 +18460,9 @@ enum { /* extraction utilities */ -#define NANOMIPS_EXTRACT_RD(op) ((op >> 7) & 0x7) -#define NANOMIPS_EXTRACT_RS(op) ((op >> 4) & 0x7) -#define NANOMIPS_EXTRACT_RS2(op) uMIPS_RS(op) -#define NANOMIPS_EXTRACT_RS1(op) ((op >> 1) & 0x7) +#define NANOMIPS_EXTRACT_RT3(op) ((op >> 7) & 0x7) +#define NANOMIPS_EXTRACT_RS3(op) ((op >> 4) & 0x7) +#define NANOMIPS_EXTRACT_RD3(op) ((op >> 1) & 0x7) #define NANOMIPS_EXTRACT_RD5(op) ((op >> 5) & 0x1f) #define NANOMIPS_EXTRACT_RS5(op) (op & 0x1f) @@ -18502,16 +18501,6 @@ static inline int decode_gpr_gpr4_zero(int r) } -/* extraction utilities */ - -#define NANOMIPS_EXTRACT_RD(op) ((op >> 7) & 0x7) -#define NANOMIPS_EXTRACT_RS(op) ((op >> 4) & 0x7) -#define NANOMIPS_EXTRACT_RS2(op) uMIPS_RS(op) -#define NANOMIPS_EXTRACT_RS1(op) ((op >> 1) & 0x7) -#define NANOMIPS_EXTRACT_RD5(op) ((op >> 5) & 0x1f) -#define NANOMIPS_EXTRACT_RS5(op) (op & 0x1f) - - static void gen_adjust_sp(DisasContext *ctx, int u) { gen_op_addr_addi(ctx, cpu_gpr[29], cpu_gpr[29], u); @@ -18570,8 +18559,8 @@ static void gen_restore(DisasContext *ctx, uint8_t rt, uint8_t count, static void gen_pool16c_nanomips_insn(DisasContext *ctx) { - int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD(ctx->opcode)); - int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS(ctx->opcode)); + int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RT3(ctx->opcode)); + int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS3(ctx->opcode)); switch (extract32(ctx->opcode, 2, 2)) { case NM_NOT16: @@ -19769,6 +19758,10 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc, goto out; } + /* branch completion */ + clear_branch_hflags(ctx); + ctx->base.is_jmp = DISAS_NORETURN; + if (bcond_compute == 0) { /* Uncoditional compact branch */ gen_goto_tb(ctx, 0, ctx->btarget); @@ -19809,6 +19802,10 @@ static void gen_compute_nanomips_pbalrsc_branch(DisasContext *ctx, int rs, tcg_gen_movi_tl(t1, ctx->base.pc_next + 4); gen_op_addr_add(ctx, btarget, t1, t0); + /* branch completion */ + clear_branch_hflags(ctx); + ctx->base.is_jmp = DISAS_NORETURN; + /* unconditional branch to register */ tcg_gen_mov_tl(cpu_PC, btarget); tcg_gen_lookup_and_goto_ptr(); @@ -19947,6 +19944,10 @@ static void gen_compute_compact_branch_nm(DisasContext *ctx, uint32_t opc, goto out; } + /* branch completion */ + clear_branch_hflags(ctx); + ctx->base.is_jmp = DISAS_NORETURN; + /* Generating branch here as compact branches don't have delay slot */ gen_goto_tb(ctx, 1, ctx->btarget); gen_set_label(fs); @@ -21561,7 +21562,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) break; case NM_SCWP: check_xnp(ctx); - gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5)); + gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5), + false); break; } break; @@ -21665,7 +21667,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) check_xnp(ctx); check_eva(ctx); check_cp0_enabled(ctx); - gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5)); + gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5), + true); break; default: generate_exception_end(ctx, EXCP_RI); @@ -21872,9 +21875,9 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx) { uint32_t op; - int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD(ctx->opcode)); - int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS(ctx->opcode)); - int rd = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS1(ctx->opcode)); + int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RT3(ctx->opcode)); + int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS3(ctx->opcode)); + int rd = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD3(ctx->opcode)); int offset; int imm; @@ -22037,7 +22040,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx) break; case NM_SB16: rt = decode_gpr_gpr3_src_store( - NANOMIPS_EXTRACT_RD(ctx->opcode)); + NANOMIPS_EXTRACT_RT3(ctx->opcode)); gen_st(ctx, OPC_SB, rt, rs, offset); break; case NM_LBU16: @@ -22056,7 +22059,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx) break; case NM_SH16: rt = decode_gpr_gpr3_src_store( - NANOMIPS_EXTRACT_RD(ctx->opcode)); + NANOMIPS_EXTRACT_RT3(ctx->opcode)); gen_st(ctx, OPC_SH, rt, rs, offset); break; case NM_LHU16: @@ -22111,14 +22114,14 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx) break; case NM_SW16: rt = decode_gpr_gpr3_src_store( - NANOMIPS_EXTRACT_RD(ctx->opcode)); - rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS(ctx->opcode)); + NANOMIPS_EXTRACT_RT3(ctx->opcode)); + rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS3(ctx->opcode)); offset = extract32(ctx->opcode, 0, 4) << 2; gen_st(ctx, OPC_SW, rt, rs, offset); break; case NM_SWGP16: rt = decode_gpr_gpr3_src_store( - NANOMIPS_EXTRACT_RD(ctx->opcode)); + NANOMIPS_EXTRACT_RT3(ctx->opcode)); offset = extract32(ctx->opcode, 0, 7) << 2; gen_st(ctx, OPC_SW, rt, 28, offset); break; @@ -29894,7 +29897,7 @@ bool cpu_supports_cps_smp(const char *cpu_type) return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0; } -bool cpu_supports_isa(const char *cpu_type, unsigned int isa) +bool cpu_supports_isa(const char *cpu_type, uint64_t isa) { const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type)); return (mcc->cpu_def->insn_flags & isa) != 0; diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.inc.c index acab097..bf559af 100644 --- a/target/mips/translate_init.inc.c +++ b/target/mips/translate_init.inc.c @@ -722,6 +722,46 @@ const mips_def_t mips_defs[] = .mmu_type = MMU_TYPE_R4000, }, { + .name = "I6500", + .CP0_PRid = 0x1B000, + .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | + (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) | + (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) | + (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | + (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) | + (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | + (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt), + .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) | + (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist), + .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) | + (1 << CP0C5_LLB) | (1 << CP0C5_MRP), + .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) | + (1 << CP0C5_FRE) | (1 << CP0C5_UFE), + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 0, + .SYNCI_Step = 64, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x30D8FFFF, + .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) | + (1U << CP0PG_RIE), + .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA), + .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG), + .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) | + (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | + (1 << FCR0_S) | (0x03 << FCR0_PRID) | (0x0 << FCR0_REV), + .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), + .CP1_fcr31_rw_bitmask = 0x0103FFFF, + .MSAIR = 0x03 << MSAIR_ProcID, + .SEGBITS = 48, + .PABITS = 48, + .insn_flags = CPU_MIPS64R6 | ASE_MSA, + .mmu_type = MMU_TYPE_R4000, + }, + { .name = "Loongson-2E", .CP0_PRid = 0x6302, /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */ |