aboutsummaryrefslogtreecommitdiff
path: root/target/rx/translate.c
diff options
context:
space:
mode:
Diffstat (limited to 'target/rx/translate.c')
-rw-r--r--target/rx/translate.c84
1 files changed, 36 insertions, 48 deletions
diff --git a/target/rx/translate.c b/target/rx/translate.c
index 6624414..70fad98 100644
--- a/target/rx/translate.c
+++ b/target/rx/translate.c
@@ -456,7 +456,7 @@ static bool trans_MOV_ir(DisasContext *ctx, arg_MOV_ir *a)
static bool trans_MOV_im(DisasContext *ctx, arg_MOV_im *a)
{
TCGv imm, mem;
- imm = tcg_const_i32(a->imm);
+ imm = tcg_constant_i32(a->imm);
mem = tcg_temp_new();
tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz);
rx_gen_st(a->sz, imm, mem);
@@ -729,8 +729,8 @@ static inline void stcond(TCGCond cond, int rd, int imm)
{
TCGv z;
TCGv _imm;
- z = tcg_const_i32(0);
- _imm = tcg_const_i32(imm);
+ z = tcg_constant_i32(0);
+ _imm = tcg_constant_i32(imm);
tcg_gen_movcond_i32(cond, cpu_regs[rd], cpu_psw_z, z,
_imm, cpu_regs[rd]);
}
@@ -815,7 +815,7 @@ static inline void rx_gen_op_rrr(op3fn opr, int dst, int src, int src2)
static inline void rx_gen_op_irr(op3fn opr, int dst, int src, uint32_t src2)
{
- TCGv imm = tcg_const_i32(src2);
+ TCGv imm = tcg_constant_i32(src2);
opr(cpu_regs[dst], cpu_regs[src], imm);
}
@@ -967,14 +967,13 @@ static bool trans_NEG_rr(DisasContext *ctx, arg_NEG_rr *a)
/* ret = arg1 + arg2 + psw_c */
static void rx_adc(TCGv ret, TCGv arg1, TCGv arg2)
{
- TCGv z;
- z = tcg_const_i32(0);
+ TCGv z = tcg_constant_i32(0);
tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, arg1, z, cpu_psw_c, z);
tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, cpu_psw_s, cpu_psw_c, arg2, z);
- tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1);
- tcg_gen_xor_i32(z, arg1, arg2);
- tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, z);
+ tcg_gen_xor_i32(cpu_psw_z, arg1, arg2);
+ tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, cpu_psw_z);
+ tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
tcg_gen_mov_i32(ret, cpu_psw_s);
}
@@ -1006,13 +1005,12 @@ static bool trans_ADC_mr(DisasContext *ctx, arg_ADC_mr *a)
/* ret = arg1 + arg2 */
static void rx_add(TCGv ret, TCGv arg1, TCGv arg2)
{
- TCGv z;
- z = tcg_const_i32(0);
+ TCGv z = tcg_constant_i32(0);
tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, arg1, z, arg2, z);
- tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1);
- tcg_gen_xor_i32(z, arg1, arg2);
- tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, z);
+ tcg_gen_xor_i32(cpu_psw_z, arg1, arg2);
+ tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, cpu_psw_z);
+ tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
tcg_gen_mov_i32(ret, cpu_psw_s);
}
@@ -1042,23 +1040,23 @@ static bool trans_ADD_rrr(DisasContext *ctx, arg_ADD_rrr *a)
/* ret = arg1 - arg2 */
static void rx_sub(TCGv ret, TCGv arg1, TCGv arg2)
{
- TCGv temp;
tcg_gen_sub_i32(cpu_psw_s, arg1, arg2);
- tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
tcg_gen_setcond_i32(TCG_COND_GEU, cpu_psw_c, arg1, arg2);
tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1);
- temp = tcg_temp_new_i32();
- tcg_gen_xor_i32(temp, arg1, arg2);
- tcg_gen_and_i32(cpu_psw_o, cpu_psw_o, temp);
+ tcg_gen_xor_i32(cpu_psw_z, arg1, arg2);
+ tcg_gen_and_i32(cpu_psw_o, cpu_psw_o, cpu_psw_z);
+ tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
/* CMP not required return */
if (ret) {
tcg_gen_mov_i32(ret, cpu_psw_s);
}
}
+
static void rx_cmp(TCGv dummy, TCGv arg1, TCGv arg2)
{
rx_sub(NULL, arg1, arg2);
}
+
/* ret = arg1 - arg2 - !psw_c */
/* -> ret = arg1 + ~arg2 + psw_c */
static void rx_sbb(TCGv ret, TCGv arg1, TCGv arg2)
@@ -1126,21 +1124,11 @@ static bool trans_SBB_mr(DisasContext *ctx, arg_SBB_mr *a)
return true;
}
-static void rx_abs(TCGv ret, TCGv arg1)
-{
- TCGv neg;
- TCGv zero;
- neg = tcg_temp_new();
- zero = tcg_const_i32(0);
- tcg_gen_neg_i32(neg, arg1);
- tcg_gen_movcond_i32(TCG_COND_LT, ret, arg1, zero, neg, arg1);
-}
-
/* abs rd */
/* abs rs, rd */
static bool trans_ABS_rr(DisasContext *ctx, arg_ABS_rr *a)
{
- rx_gen_op_rr(rx_abs, a->rd, a->rs);
+ rx_gen_op_rr(tcg_gen_abs_i32, a->rd, a->rs);
return true;
}
@@ -1200,7 +1188,7 @@ static bool trans_MUL_rrr(DisasContext *ctx, arg_MUL_rrr *a)
/* emul #imm, rd */
static bool trans_EMUL_ir(DisasContext *ctx, arg_EMUL_ir *a)
{
- TCGv imm = tcg_const_i32(a->imm);
+ TCGv imm = tcg_constant_i32(a->imm);
if (a->rd > 14) {
qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd);
}
@@ -1227,7 +1215,7 @@ static bool trans_EMUL_mr(DisasContext *ctx, arg_EMUL_mr *a)
/* emulu #imm, rd */
static bool trans_EMULU_ir(DisasContext *ctx, arg_EMULU_ir *a)
{
- TCGv imm = tcg_const_i32(a->imm);
+ TCGv imm = tcg_constant_i32(a->imm);
if (a->rd > 14) {
qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd);
}
@@ -1325,10 +1313,10 @@ static bool trans_SHLL_rr(DisasContext *ctx, arg_SHLL_rr *a)
done = gen_new_label();
/* if (cpu_regs[a->rs]) { */
tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_regs[a->rs], 0, noshift);
- count = tcg_const_i32(32);
+ count = tcg_temp_new();
tmp = tcg_temp_new();
tcg_gen_andi_i32(tmp, cpu_regs[a->rs], 31);
- tcg_gen_sub_i32(count, count, tmp);
+ tcg_gen_sub_i32(count, tcg_constant_i32(32), tmp);
tcg_gen_sar_i32(cpu_psw_c, cpu_regs[a->rd], count);
tcg_gen_shl_i32(cpu_regs[a->rd], cpu_regs[a->rd], tmp);
tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_o, cpu_psw_c, 0);
@@ -1597,7 +1585,7 @@ static bool trans_BRA_l(DisasContext *ctx, arg_BRA_l *a)
static inline void rx_save_pc(DisasContext *ctx)
{
- TCGv pc = tcg_const_i32(ctx->base.pc_next);
+ TCGv pc = tcg_constant_i32(ctx->base.pc_next);
push(pc);
}
@@ -1680,7 +1668,7 @@ static bool trans_SMOVB(DisasContext *ctx, arg_SMOVB *a)
#define STRING(op) \
do { \
- TCGv size = tcg_const_i32(a->sz); \
+ TCGv size = tcg_constant_i32(a->sz); \
gen_helper_##op(cpu_env, size); \
} while (0)
@@ -1811,7 +1799,7 @@ static bool trans_MVTACLO(DisasContext *ctx, arg_MVTACLO *a)
/* racw #imm */
static bool trans_RACW(DisasContext *ctx, arg_RACW *a)
{
- TCGv imm = tcg_const_i32(a->imm + 1);
+ TCGv imm = tcg_constant_i32(a->imm + 1);
gen_helper_racw(cpu_env, imm);
return true;
}
@@ -1821,7 +1809,7 @@ static bool trans_SAT(DisasContext *ctx, arg_SAT *a)
{
TCGv tmp, z;
tmp = tcg_temp_new();
- z = tcg_const_i32(0);
+ z = tcg_constant_i32(0);
/* S == 1 -> 0xffffffff / S == 0 -> 0x00000000 */
tcg_gen_sari_i32(tmp, cpu_psw_s, 31);
/* S == 1 -> 0x7fffffff / S == 0 -> 0x80000000 */
@@ -1843,7 +1831,7 @@ static bool trans_SATR(DisasContext *ctx, arg_SATR *a)
static bool cat3(trans_, name, _ir)(DisasContext *ctx, \
cat3(arg_, name, _ir) * a) \
{ \
- TCGv imm = tcg_const_i32(li(ctx, 0)); \
+ TCGv imm = tcg_constant_i32(li(ctx, 0)); \
gen_helper_##op(cpu_regs[a->rd], cpu_env, \
cpu_regs[a->rd], imm); \
return true; \
@@ -1877,7 +1865,7 @@ FOP(FDIV, fdiv)
/* fcmp #imm, rd */
static bool trans_FCMP_ir(DisasContext *ctx, arg_FCMP_ir * a)
{
- TCGv imm = tcg_const_i32(li(ctx, 0));
+ TCGv imm = tcg_constant_i32(li(ctx, 0));
gen_helper_fcmp(cpu_env, cpu_regs[a->rd], imm);
return true;
}
@@ -1974,7 +1962,7 @@ static inline void rx_bnotr(TCGv reg, TCGv mask)
{ \
TCGv mask, mem, addr; \
mem = tcg_temp_new(); \
- mask = tcg_const_i32(1 << a->imm); \
+ mask = tcg_constant_i32(1 << a->imm); \
addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \
cat3(rx_, op, m)(addr, mask); \
return true; \
@@ -1983,7 +1971,7 @@ static inline void rx_bnotr(TCGv reg, TCGv mask)
cat3(arg_, name, _ir) * a) \
{ \
TCGv mask; \
- mask = tcg_const_i32(1 << a->imm); \
+ mask = tcg_constant_i32(1 << a->imm); \
cat3(rx_, op, r)(cpu_regs[a->rd], mask); \
return true; \
} \
@@ -1991,10 +1979,10 @@ static inline void rx_bnotr(TCGv reg, TCGv mask)
cat3(arg_, name, _rr) * a) \
{ \
TCGv mask, b; \
- mask = tcg_const_i32(1); \
+ mask = tcg_temp_new(); \
b = tcg_temp_new(); \
tcg_gen_andi_i32(b, cpu_regs[a->rs], 31); \
- tcg_gen_shl_i32(mask, mask, b); \
+ tcg_gen_shl_i32(mask, tcg_constant_i32(1), b); \
cat3(rx_, op, r)(cpu_regs[a->rd], mask); \
return true; \
} \
@@ -2002,10 +1990,10 @@ static inline void rx_bnotr(TCGv reg, TCGv mask)
cat3(arg_, name, _rm) * a) \
{ \
TCGv mask, mem, addr, b; \
- mask = tcg_const_i32(1); \
+ mask = tcg_temp_new(); \
b = tcg_temp_new(); \
tcg_gen_andi_i32(b, cpu_regs[a->rd], 7); \
- tcg_gen_shl_i32(mask, mask, b); \
+ tcg_gen_shl_i32(mask, tcg_constant_i32(1), b); \
mem = tcg_temp_new(); \
addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \
cat3(rx_, op, m)(addr, mask); \
@@ -2128,7 +2116,7 @@ static bool trans_MVTC_i(DisasContext *ctx, arg_MVTC_i *a)
{
TCGv imm;
- imm = tcg_const_i32(a->imm);
+ imm = tcg_constant_i32(a->imm);
move_to_cr(ctx, imm, a->cr);
return true;
}
@@ -2190,7 +2178,7 @@ static bool trans_INT(DisasContext *ctx, arg_INT *a)
TCGv vec;
tcg_debug_assert(a->imm < 0x100);
- vec = tcg_const_i32(a->imm);
+ vec = tcg_constant_i32(a->imm);
tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next);
gen_helper_rxint(cpu_env, vec);
ctx->base.is_jmp = DISAS_NORETURN;
generated by cgit v1.1 at 2025-02-07 23:24:12 +0000