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-rw-r--r--target/riscv/csr.c8
1 files changed, 0 insertions, 8 deletions
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index d81f466..4a7078f 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1494,10 +1494,6 @@ static RISCVException write_mtvec(CPURISCVState *env, int csrno,
static RISCVException read_mcountinhibit(CPURISCVState *env, int csrno,
target_ulong *val)
{
- if (env->priv_ver < PRIV_VERSION_1_11_0) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
-
*val = env->mcountinhibit;
return RISCV_EXCP_NONE;
}
@@ -1508,10 +1504,6 @@ static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno,
int cidx;
PMUCTRState *counter;
- if (env->priv_ver < PRIV_VERSION_1_11_0) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
-
env->mcountinhibit = val;
/* Check if any other counter is also monitoring cycles/instructions */