diff options
Diffstat (limited to 'target/riscv')
-rw-r--r-- | target/riscv/cpu-param.h | 23 | ||||
-rw-r--r-- | target/riscv/cpu.c | 3 | ||||
-rw-r--r-- | target/riscv/cpu.h | 34 | ||||
-rw-r--r-- | target/riscv/cpu_helper.c | 10 | ||||
-rw-r--r-- | target/riscv/csr.c | 12 | ||||
-rw-r--r-- | target/riscv/op_helper.c | 7 |
6 files changed, 43 insertions, 46 deletions
diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h new file mode 100644 index 0000000..664fc1d --- /dev/null +++ b/target/riscv/cpu-param.h @@ -0,0 +1,23 @@ +/* + * RISC-V cpu parameters for qemu. + * + * Copyright (c) 2017-2018 SiFive, Inc. + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef RISCV_CPU_PARAM_H +#define RISCV_CPU_PARAM_H 1 + +#if defined(TARGET_RISCV64) +# define TARGET_LONG_BITS 64 +# define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */ +# define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */ +#elif defined(TARGET_RISCV32) +# define TARGET_LONG_BITS 32 +# define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */ +# define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */ +#endif +#define TARGET_PAGE_BITS 12 /* 4 KiB Pages */ +#define NB_MMU_MODES 4 + +#endif diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e298799..86fd869 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -367,10 +367,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) static void riscv_cpu_init(Object *obj) { - CPUState *cs = CPU(obj); RISCVCPU *cpu = RISCV_CPU(obj); - cs->env_ptr = &cpu->env; + cpu_set_cpustate_pointers(cpu); } static const VMStateDescription vmstate_riscv_cpu = { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 74e726c..a935b17 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -20,27 +20,13 @@ #ifndef RISCV_CPU_H #define RISCV_CPU_H -/* QEMU addressing/paging config */ -#define TARGET_PAGE_BITS 12 /* 4 KiB Pages */ -#if defined(TARGET_RISCV64) -#define TARGET_LONG_BITS 64 -#define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */ -#define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */ -#elif defined(TARGET_RISCV32) -#define TARGET_LONG_BITS 32 -#define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */ -#define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */ -#endif - -#define TCG_GUEST_DEFAULT_MO 0 - -#define CPUArchState struct CPURISCVState - #include "qemu-common.h" #include "qom/cpu.h" #include "exec/cpu-defs.h" #include "fpu/softfloat.h" +#define TCG_GUEST_DEFAULT_MO 0 + #define TYPE_RISCV_CPU "riscv-cpu" #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU @@ -98,7 +84,6 @@ enum { #define TRANSLATE_FAIL 1 #define TRANSLATE_SUCCESS 0 -#define NB_MMU_MODES 4 #define MMU_USER_IDX 3 #define MAX_RISCV_PMPS (16) @@ -186,9 +171,6 @@ struct CPURISCVState { float_status fp_status; - /* QEMU */ - CPU_COMMON - /* Fields from here on are preserved across CPU reset. */ QEMUTimer *timer; /* Internal timer */ }; @@ -225,6 +207,7 @@ typedef struct RISCVCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ + CPUNegativeOffsetState neg; CPURISCVState env; /* Configuration Settings */ @@ -236,11 +219,6 @@ typedef struct RISCVCPU { } cfg; } RISCVCPU; -static inline RISCVCPU *riscv_env_get_cpu(CPURISCVState *env) -{ - return container_of(env, RISCVCPU, env); -} - static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) { return (env->misa & ext) != 0; @@ -259,9 +237,6 @@ extern const char * const riscv_fpr_regnames[]; extern const char * const riscv_excp_names[]; extern const char * const riscv_intr_names[]; -#define ENV_GET_CPU(e) CPU(riscv_env_get_cpu(e)) -#define ENV_OFFSET offsetof(RISCVCPU, env) - void riscv_cpu_do_interrupt(CPUState *cpu); int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); @@ -349,6 +324,9 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); +typedef CPURISCVState CPUArchState; +typedef RISCVCPU ArchCPU; + #include "exec/cpu-all.h" #endif /* RISCV_CPU_H */ diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index c577a26..8b6754b 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -89,14 +89,12 @@ struct CpuAsyncInfo { static void riscv_cpu_update_mip_irqs_async(CPUState *target_cpu_state, run_on_cpu_data data) { - CPURISCVState *env = &RISCV_CPU(target_cpu_state)->env; - RISCVCPU *cpu = riscv_env_get_cpu(env); struct CpuAsyncInfo *info = (struct CpuAsyncInfo *) data.host_ptr; if (info->new_mip) { - cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); + cpu_interrupt(target_cpu_state, CPU_INTERRUPT_HARD); } else { - cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); + cpu_reset_interrupt(target_cpu_state, CPU_INTERRUPT_HARD); } g_free(info); @@ -212,7 +210,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, } } - CPUState *cs = CPU(riscv_env_get_cpu(env)); + CPUState *cs = env_cpu(env); int va_bits = PGSHIFT + levels * ptidxbits; target_ulong mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; target_ulong masked_msbs = (addr >> (va_bits - 1)) & mask; @@ -341,7 +339,7 @@ restart: static void raise_mmu_exception(CPURISCVState *env, target_ulong address, MMUAccessType access_type) { - CPUState *cs = CPU(riscv_env_get_cpu(env)); + CPUState *cs = env_cpu(env); int page_fault_exceptions = (env->priv_ver >= PRIV_VERSION_1_10_0) && get_field(env->satp, SATP_MODE) != VM_1_10_MBARE; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index f9e2910..c67d29e 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -296,7 +296,7 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) if (env->priv_ver <= PRIV_VERSION_1_09_1) { if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_VM)) { - tlb_flush(CPU(riscv_env_get_cpu(env))); + tlb_flush(env_cpu(env)); } mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | @@ -307,7 +307,7 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) if (env->priv_ver >= PRIV_VERSION_1_10_0) { if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | MSTATUS_MPRV | MSTATUS_SUM)) { - tlb_flush(CPU(riscv_env_get_cpu(env))); + tlb_flush(env_cpu(env)); } mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | @@ -382,7 +382,7 @@ static int write_misa(CPURISCVState *env, int csrno, target_ulong val) /* flush translation cache */ if (val != env->misa) { - tb_flush(CPU(riscv_env_get_cpu(env))); + tb_flush(env_cpu(env)); } env->misa = val; @@ -549,7 +549,7 @@ static int write_mbadaddr(CPURISCVState *env, int csrno, target_ulong val) static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, target_ulong write_mask) { - RISCVCPU *cpu = riscv_env_get_cpu(env); + RISCVCPU *cpu = env_archcpu(env); /* Allow software control of delegable interrupts not claimed by hardware */ target_ulong mask = write_mask & delegable_ints & ~env->miclaim; uint32_t old_mip; @@ -712,7 +712,7 @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val) return 0; } if (env->priv_ver <= PRIV_VERSION_1_09_1 && (val ^ env->sptbr)) { - tlb_flush(CPU(riscv_env_get_cpu(env))); + tlb_flush(env_cpu(env)); env->sptbr = val & (((target_ulong) 1 << (TARGET_PHYS_ADDR_SPACE_BITS - PGSHIFT)) - 1); } @@ -724,7 +724,7 @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val) return -1; } else { if((val ^ env->satp) & SATP_ASID) { - tlb_flush(CPU(riscv_env_get_cpu(env))); + tlb_flush(env_cpu(env)); } env->satp = val; } diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 644d0fb..331cc36 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -28,7 +28,7 @@ void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, uint32_t exception, uintptr_t pc) { - CPUState *cs = CPU(riscv_env_get_cpu(env)); + CPUState *cs = env_cpu(env); qemu_log_mask(CPU_LOG_INT, "%s: %d\n", __func__, exception); cs->exception_index = exception; cpu_loop_exit_restore(cs, pc); @@ -128,7 +128,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb) void helper_wfi(CPURISCVState *env) { - CPUState *cs = CPU(riscv_env_get_cpu(env)); + CPUState *cs = env_cpu(env); if (env->priv == PRV_S && env->priv_ver >= PRIV_VERSION_1_10_0 && @@ -143,8 +143,7 @@ void helper_wfi(CPURISCVState *env) void helper_tlb_flush(CPURISCVState *env) { - RISCVCPU *cpu = riscv_env_get_cpu(env); - CPUState *cs = CPU(cpu); + CPUState *cs = env_cpu(env); if (!(env->priv >= PRV_S) || (env->priv == PRV_S && env->priv_ver >= PRIV_VERSION_1_10_0 && |