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-rw-r--r--target/riscv/internals.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index f1a546d..b15ad39 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -38,6 +38,10 @@ target_ulong fclass_d(uint64_t frs1);
#define SEW32 2
#define SEW64 3
+#ifndef CONFIG_USER_ONLY
+extern const VMStateDescription vmstate_riscv_cpu;
+#endif
+
static inline uint64_t nanbox_s(float32 f)
{
return f | MAKE_64BIT_MASK(32, 32);