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Diffstat (limited to 'target/riscv/csr.c')
-rw-r--r--target/riscv/csr.c41
1 files changed, 24 insertions, 17 deletions
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 58499b5..ea75853 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1311,11 +1311,9 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
}
if (xl != MXL_RV32 || env->debugger) {
- /*
- * RV32: MPV and GVA are not in mstatus. The current plan is to
- * add them to mstatush. For now, we just don't support it.
- */
- mask |= MSTATUS_MPV | MSTATUS_GVA;
+ if (riscv_has_ext(env, RVH)) {
+ mask |= MSTATUS_MPV | MSTATUS_GVA;
+ }
if ((val & MSTATUS64_UXL) != 0) {
mask |= MSTATUS64_UXL;
}
@@ -1323,10 +1321,6 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
mstatus = (mstatus & ~mask) | (val & mask);
- if (xl > MXL_RV32) {
- /* SXL field is for now read only */
- mstatus = set_field(mstatus, MSTATUS64_SXL, xl);
- }
env->mstatus = mstatus;
/*
@@ -1335,8 +1329,9 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
*/
if (env->debugger) {
env->xl = cpu_recompute_xl(env);
- riscv_cpu_update_mask(env);
}
+
+ riscv_cpu_update_mask(env);
return RISCV_EXCP_NONE;
}
@@ -1351,7 +1346,7 @@ static RISCVException write_mstatush(CPURISCVState *env, int csrno,
target_ulong val)
{
uint64_t valh = (uint64_t)val << 32;
- uint64_t mask = MSTATUS_MPV | MSTATUS_GVA;
+ uint64_t mask = riscv_has_ext(env, RVH) ? MSTATUS_MPV | MSTATUS_GVA : 0;
env->mstatus = (env->mstatus & ~mask) | (valh & mask);
@@ -3639,7 +3634,7 @@ static RISCVException write_mpmmask(CPURISCVState *env, int csrno,
uint64_t mstatus;
env->mpmmask = val;
- if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
+ if ((cpu_address_mode(env) == PRV_M) && (env->mmte & M_PM_ENABLE)) {
env->cur_pmmask = val;
}
env->mmte |= EXT_STATUS_DIRTY;
@@ -3667,8 +3662,11 @@ static RISCVException write_spmmask(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
env->spmmask = val;
- if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
+ if ((cpu_address_mode(env) == PRV_S) && (env->mmte & S_PM_ENABLE)) {
env->cur_pmmask = val;
+ if (cpu_get_xl(env, PRV_S) == MXL_RV32) {
+ env->cur_pmmask &= UINT32_MAX;
+ }
}
env->mmte |= EXT_STATUS_DIRTY;
@@ -3695,8 +3693,11 @@ static RISCVException write_upmmask(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
env->upmmask = val;
- if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
+ if ((cpu_address_mode(env) == PRV_U) && (env->mmte & U_PM_ENABLE)) {
env->cur_pmmask = val;
+ if (cpu_get_xl(env, PRV_U) == MXL_RV32) {
+ env->cur_pmmask &= UINT32_MAX;
+ }
}
env->mmte |= EXT_STATUS_DIRTY;
@@ -3719,7 +3720,7 @@ static RISCVException write_mpmbase(CPURISCVState *env, int csrno,
uint64_t mstatus;
env->mpmbase = val;
- if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
+ if ((cpu_address_mode(env) == PRV_M) && (env->mmte & M_PM_ENABLE)) {
env->cur_pmbase = val;
}
env->mmte |= EXT_STATUS_DIRTY;
@@ -3747,8 +3748,11 @@ static RISCVException write_spmbase(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
env->spmbase = val;
- if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
+ if ((cpu_address_mode(env) == PRV_S) && (env->mmte & S_PM_ENABLE)) {
env->cur_pmbase = val;
+ if (cpu_get_xl(env, PRV_S) == MXL_RV32) {
+ env->cur_pmbase &= UINT32_MAX;
+ }
}
env->mmte |= EXT_STATUS_DIRTY;
@@ -3775,8 +3779,11 @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
env->upmbase = val;
- if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
+ if ((cpu_address_mode(env) == PRV_U) && (env->mmte & U_PM_ENABLE)) {
env->cur_pmbase = val;
+ if (cpu_get_xl(env, PRV_U) == MXL_RV32) {
+ env->cur_pmbase &= UINT32_MAX;
+ }
}
env->mmte |= EXT_STATUS_DIRTY;