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-rw-r--r--target/ppc/translate/branch-impl.c.inc2
-rw-r--r--target/ppc/translate/dfp-impl.c.inc22
-rw-r--r--target/ppc/translate/fixedpoint-impl.c.inc2
-rw-r--r--target/ppc/translate/fp-impl.c.inc50
-rw-r--r--target/ppc/translate/processor-ctrl-impl.c.inc8
-rw-r--r--target/ppc/translate/spe-impl.c.inc30
-rw-r--r--target/ppc/translate/storage-ctrl-impl.c.inc26
-rw-r--r--target/ppc/translate/vmx-impl.c.inc34
-rw-r--r--target/ppc/translate/vsx-impl.c.inc54
9 files changed, 114 insertions, 114 deletions
diff --git a/target/ppc/translate/branch-impl.c.inc b/target/ppc/translate/branch-impl.c.inc
index f9931b9..fb0fcf3 100644
--- a/target/ppc/translate/branch-impl.c.inc
+++ b/target/ppc/translate/branch-impl.c.inc
@@ -18,7 +18,7 @@ static bool trans_RFEBB(DisasContext *ctx, arg_XL_s *arg)
translator_io_start(&ctx->base);
gen_update_cfar(ctx, ctx->cia);
- gen_helper_rfebb(cpu_env, cpu_gpr[arg->s]);
+ gen_helper_rfebb(tcg_env, cpu_gpr[arg->s]);
ctx->base.is_jmp = DISAS_CHAIN;
diff --git a/target/ppc/translate/dfp-impl.c.inc b/target/ppc/translate/dfp-impl.c.inc
index 62911e0..3710765 100644
--- a/target/ppc/translate/dfp-impl.c.inc
+++ b/target/ppc/translate/dfp-impl.c.inc
@@ -3,7 +3,7 @@
static inline TCGv_ptr gen_fprp_ptr(int reg)
{
TCGv_ptr r = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, vsr[reg].u64[0]));
+ tcg_gen_addi_ptr(r, tcg_env, offsetof(CPUPPCState, vsr[reg].u64[0]));
return r;
}
@@ -16,7 +16,7 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
rt = gen_fprp_ptr(a->rt); \
ra = gen_fprp_ptr(a->ra); \
rb = gen_fprp_ptr(a->rb); \
- gen_helper_##NAME(cpu_env, rt, ra, rb); \
+ gen_helper_##NAME(tcg_env, rt, ra, rb); \
if (unlikely(a->rc)) { \
gen_set_cr1_from_fpscr(ctx); \
} \
@@ -32,7 +32,7 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
ra = gen_fprp_ptr(a->ra); \
rb = gen_fprp_ptr(a->rb); \
gen_helper_##NAME(cpu_crf[a->bf], \
- cpu_env, ra, rb); \
+ tcg_env, ra, rb); \
return true; \
}
@@ -44,7 +44,7 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
REQUIRE_FPU(ctx); \
rb = gen_fprp_ptr(a->rb); \
gen_helper_##NAME(cpu_crf[a->bf], \
- cpu_env, tcg_constant_i32(a->uim), rb);\
+ tcg_env, tcg_constant_i32(a->uim), rb);\
return true; \
}
@@ -56,7 +56,7 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
REQUIRE_FPU(ctx); \
ra = gen_fprp_ptr(a->fra); \
gen_helper_##NAME(cpu_crf[a->bf], \
- cpu_env, ra, tcg_constant_i32(a->dm)); \
+ tcg_env, ra, tcg_constant_i32(a->dm)); \
return true; \
}
@@ -68,7 +68,7 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
REQUIRE_FPU(ctx); \
rt = gen_fprp_ptr(a->frt); \
rb = gen_fprp_ptr(a->frb); \
- gen_helper_##NAME(cpu_env, rt, rb, \
+ gen_helper_##NAME(tcg_env, rt, rb, \
tcg_constant_i32(a->U32F1), \
tcg_constant_i32(a->U32F2)); \
if (unlikely(a->rc)) { \
@@ -86,7 +86,7 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
rt = gen_fprp_ptr(a->frt); \
ra = gen_fprp_ptr(a->fra); \
rb = gen_fprp_ptr(a->frb); \
- gen_helper_##NAME(cpu_env, rt, ra, rb, \
+ gen_helper_##NAME(tcg_env, rt, ra, rb, \
tcg_constant_i32(a->I32FLD)); \
if (unlikely(a->rc)) { \
gen_set_cr1_from_fpscr(ctx); \
@@ -102,7 +102,7 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
REQUIRE_FPU(ctx); \
rt = gen_fprp_ptr(a->rt); \
rb = gen_fprp_ptr(a->rb); \
- gen_helper_##NAME(cpu_env, rt, rb); \
+ gen_helper_##NAME(tcg_env, rt, rb); \
if (unlikely(a->rc)) { \
gen_set_cr1_from_fpscr(ctx); \
} \
@@ -117,7 +117,7 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
REQUIRE_FPU(ctx); \
rt = gen_fprp_ptr(a->rt); \
rx = gen_fprp_ptr(a->FPRFLD); \
- gen_helper_##NAME(cpu_env, rt, rx, \
+ gen_helper_##NAME(tcg_env, rt, rx, \
tcg_constant_i32(a->I32FLD)); \
if (unlikely(a->rc)) { \
gen_set_cr1_from_fpscr(ctx); \
@@ -188,7 +188,7 @@ static bool trans_DCFFIXQQ(DisasContext *ctx, arg_DCFFIXQQ *a)
rt = gen_fprp_ptr(a->frtp);
rb = gen_avr_ptr(a->vrb);
- gen_helper_DCFFIXQQ(cpu_env, rt, rb);
+ gen_helper_DCFFIXQQ(tcg_env, rt, rb);
return true;
}
@@ -203,7 +203,7 @@ static bool trans_DCTFIXQQ(DisasContext *ctx, arg_DCTFIXQQ *a)
rt = gen_avr_ptr(a->vrt);
rb = gen_fprp_ptr(a->frbp);
- gen_helper_DCTFIXQQ(cpu_env, rt, rb);
+ gen_helper_DCTFIXQQ(tcg_env, rt, rb);
return true;
}
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 7ff7e1e..51c6fa7 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -517,7 +517,7 @@ static bool do_hash(DisasContext *ctx, arg_X *a, bool priv,
}
ea = do_ea_calc(ctx, a->ra, tcg_constant_tl(a->rt));
- helper(cpu_env, ea, cpu_gpr[a->ra], cpu_gpr[a->rb]);
+ helper(tcg_env, ea, cpu_gpr[a->ra], cpu_gpr[a->rb]);
return true;
}
diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc
index 874774e..189cd8c 100644
--- a/target/ppc/translate/fp-impl.c.inc
+++ b/target/ppc/translate/fp-impl.c.inc
@@ -6,13 +6,13 @@
static inline void gen_reset_fpstatus(void)
{
- gen_helper_reset_fpstatus(cpu_env);
+ gen_helper_reset_fpstatus(tcg_env);
}
static inline void gen_compute_fprf_float64(TCGv_i64 arg)
{
- gen_helper_compute_fprf_float64(cpu_env, arg);
- gen_helper_float_check_status(cpu_env);
+ gen_helper_compute_fprf_float64(tcg_env, arg);
+ gen_helper_float_check_status(tcg_env);
}
#if defined(TARGET_PPC64)
@@ -49,7 +49,7 @@ static void gen_f##name(DisasContext *ctx) \
get_fpr(t0, rA(ctx->opcode)); \
get_fpr(t1, rC(ctx->opcode)); \
get_fpr(t2, rB(ctx->opcode)); \
- gen_helper_f##name(t3, cpu_env, t0, t1, t2); \
+ gen_helper_f##name(t3, tcg_env, t0, t1, t2); \
set_fpr(rD(ctx->opcode), t3); \
if (set_fprf) { \
gen_compute_fprf_float64(t3); \
@@ -79,7 +79,7 @@ static void gen_f##name(DisasContext *ctx) \
gen_reset_fpstatus(); \
get_fpr(t0, rA(ctx->opcode)); \
get_fpr(t1, rB(ctx->opcode)); \
- gen_helper_f##name(t2, cpu_env, t0, t1); \
+ gen_helper_f##name(t2, tcg_env, t0, t1); \
set_fpr(rD(ctx->opcode), t2); \
if (set_fprf) { \
gen_compute_fprf_float64(t2); \
@@ -108,7 +108,7 @@ static void gen_f##name(DisasContext *ctx) \
gen_reset_fpstatus(); \
get_fpr(t0, rA(ctx->opcode)); \
get_fpr(t1, rC(ctx->opcode)); \
- gen_helper_f##name(t2, cpu_env, t0, t1); \
+ gen_helper_f##name(t2, tcg_env, t0, t1); \
set_fpr(rD(ctx->opcode), t2); \
if (set_fprf) { \
gen_compute_fprf_float64(t2); \
@@ -134,12 +134,12 @@ static void gen_f##name(DisasContext *ctx) \
t1 = tcg_temp_new_i64(); \
gen_reset_fpstatus(); \
get_fpr(t0, rB(ctx->opcode)); \
- gen_helper_f##name(t1, cpu_env, t0); \
+ gen_helper_f##name(t1, tcg_env, t0); \
set_fpr(rD(ctx->opcode), t1); \
if (set_fprf) { \
- gen_helper_compute_fprf_float64(cpu_env, t1); \
+ gen_helper_compute_fprf_float64(tcg_env, t1); \
} \
- gen_helper_float_check_status(cpu_env); \
+ gen_helper_float_check_status(tcg_env); \
if (unlikely(Rc(ctx->opcode) != 0)) { \
gen_set_cr1_from_fpscr(ctx); \
} \
@@ -158,7 +158,7 @@ static void gen_f##name(DisasContext *ctx) \
t1 = tcg_temp_new_i64(); \
gen_reset_fpstatus(); \
get_fpr(t0, rB(ctx->opcode)); \
- gen_helper_f##name(t1, cpu_env, t0); \
+ gen_helper_f##name(t1, tcg_env, t0); \
set_fpr(rD(ctx->opcode), t1); \
if (set_fprf) { \
gen_compute_fprf_float64(t1); \
@@ -197,7 +197,7 @@ static void gen_frsqrtes(DisasContext *ctx)
t1 = tcg_temp_new_i64();
gen_reset_fpstatus();
get_fpr(t0, rB(ctx->opcode));
- gen_helper_frsqrtes(t1, cpu_env, t0);
+ gen_helper_frsqrtes(t1, tcg_env, t0);
set_fpr(rD(ctx->opcode), t1);
gen_compute_fprf_float64(t1);
if (unlikely(Rc(ctx->opcode) != 0)) {
@@ -245,7 +245,7 @@ static bool do_helper_fsqrt(DisasContext *ctx, arg_A_tb *a,
gen_reset_fpstatus();
get_fpr(t0, a->frb);
- helper(t1, cpu_env, t0);
+ helper(t1, tcg_env, t0);
set_fpr(a->frt, t1);
gen_compute_fprf_float64(t1);
if (unlikely(a->rc != 0)) {
@@ -351,8 +351,8 @@ static void gen_fcmpo(DisasContext *ctx)
crf = tcg_constant_i32(crfD(ctx->opcode));
get_fpr(t0, rA(ctx->opcode));
get_fpr(t1, rB(ctx->opcode));
- gen_helper_fcmpo(cpu_env, t0, t1, crf);
- gen_helper_float_check_status(cpu_env);
+ gen_helper_fcmpo(tcg_env, t0, t1, crf);
+ gen_helper_float_check_status(tcg_env);
}
/* fcmpu */
@@ -371,8 +371,8 @@ static void gen_fcmpu(DisasContext *ctx)
crf = tcg_constant_i32(crfD(ctx->opcode));
get_fpr(t0, rA(ctx->opcode));
get_fpr(t1, rB(ctx->opcode));
- gen_helper_fcmpu(cpu_env, t0, t1, crf);
- gen_helper_float_check_status(cpu_env);
+ gen_helper_fcmpu(tcg_env, t0, t1, crf);
+ gen_helper_float_check_status(tcg_env);
}
/*** Floating-point move ***/
@@ -542,7 +542,7 @@ static void gen_mcrfs(DisasContext *ctx)
~((0xF << shift) & FP_EX_CLEAR_BITS));
/* FEX and VX need to be updated, so don't set fpscr directly */
tmask = tcg_constant_i32(1 << nibble);
- gen_helper_store_fpscr(cpu_env, tnew_fpscr, tmask);
+ gen_helper_store_fpscr(tcg_env, tnew_fpscr, tmask);
}
static TCGv_i64 place_from_fpscr(int rt, uint64_t mask)
@@ -565,7 +565,7 @@ static void store_fpscr_masked(TCGv_i64 fpscr, uint64_t clear_mask,
tcg_gen_andi_i64(fpscr_masked, fpscr, ~clear_mask);
tcg_gen_or_i64(fpscr_masked, fpscr_masked, set_mask);
- gen_helper_store_fpscr(cpu_env, fpscr_masked, st_mask);
+ gen_helper_store_fpscr(tcg_env, fpscr_masked, st_mask);
}
static bool trans_MFFS_ISA207(DisasContext *ctx, arg_X_t_rc *a)
@@ -691,7 +691,7 @@ static void gen_mtfsb0(DisasContext *ctx)
crb = 31 - crbD(ctx->opcode);
gen_reset_fpstatus();
if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
- gen_helper_fpscr_clrbit(cpu_env, tcg_constant_i32(crb));
+ gen_helper_fpscr_clrbit(tcg_env, tcg_constant_i32(crb));
}
if (unlikely(Rc(ctx->opcode) != 0)) {
tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
@@ -711,14 +711,14 @@ static void gen_mtfsb1(DisasContext *ctx)
crb = 31 - crbD(ctx->opcode);
/* XXX: we pretend we can only do IEEE floating-point computations */
if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
- gen_helper_fpscr_setbit(cpu_env, tcg_constant_i32(crb));
+ gen_helper_fpscr_setbit(tcg_env, tcg_constant_i32(crb));
}
if (unlikely(Rc(ctx->opcode) != 0)) {
tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
}
/* We can raise a deferred exception */
- gen_helper_fpscr_check_status(cpu_env);
+ gen_helper_fpscr_check_status(tcg_env);
}
/* mtfsf */
@@ -748,13 +748,13 @@ static void gen_mtfsf(DisasContext *ctx)
}
t1 = tcg_temp_new_i64();
get_fpr(t1, rB(ctx->opcode));
- gen_helper_store_fpscr(cpu_env, t1, t0);
+ gen_helper_store_fpscr(tcg_env, t1, t0);
if (unlikely(Rc(ctx->opcode) != 0)) {
tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
}
/* We can raise a deferred exception */
- gen_helper_fpscr_check_status(cpu_env);
+ gen_helper_fpscr_check_status(tcg_env);
}
/* mtfsfi */
@@ -777,13 +777,13 @@ static void gen_mtfsfi(DisasContext *ctx)
sh = (8 * w) + 7 - bf;
t0 = tcg_constant_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
t1 = tcg_constant_i32(1 << sh);
- gen_helper_store_fpscr(cpu_env, t0, t1);
+ gen_helper_store_fpscr(tcg_env, t0, t1);
if (unlikely(Rc(ctx->opcode) != 0)) {
tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
}
/* We can raise a deferred exception */
- gen_helper_fpscr_check_status(cpu_env);
+ gen_helper_fpscr_check_status(tcg_env);
}
static void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 dest, TCGv addr)
diff --git a/target/ppc/translate/processor-ctrl-impl.c.inc b/target/ppc/translate/processor-ctrl-impl.c.inc
index cc7a50d..0142801 100644
--- a/target/ppc/translate/processor-ctrl-impl.c.inc
+++ b/target/ppc/translate/processor-ctrl-impl.c.inc
@@ -35,9 +35,9 @@ static bool trans_MSGCLR(DisasContext *ctx, arg_X_rb *a)
#if !defined(CONFIG_USER_ONLY)
if (is_book3s_arch2x(ctx)) {
- gen_helper_book3s_msgclr(cpu_env, cpu_gpr[a->rb]);
+ gen_helper_book3s_msgclr(tcg_env, cpu_gpr[a->rb]);
} else {
- gen_helper_msgclr(cpu_env, cpu_gpr[a->rb]);
+ gen_helper_msgclr(tcg_env, cpu_gpr[a->rb]);
}
#else
qemu_build_not_reached();
@@ -75,7 +75,7 @@ static bool trans_MSGCLRP(DisasContext *ctx, arg_X_rb *a)
REQUIRE_INSNS_FLAGS2(ctx, ISA207S);
REQUIRE_SV(ctx);
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
- gen_helper_book3s_msgclrp(cpu_env, cpu_gpr[a->rb]);
+ gen_helper_book3s_msgclrp(tcg_env, cpu_gpr[a->rb]);
#else
qemu_build_not_reached();
#endif
@@ -88,7 +88,7 @@ static bool trans_MSGSNDP(DisasContext *ctx, arg_X_rb *a)
REQUIRE_INSNS_FLAGS2(ctx, ISA207S);
REQUIRE_SV(ctx);
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
- gen_helper_book3s_msgsndp(cpu_env, cpu_gpr[a->rb]);
+ gen_helper_book3s_msgsndp(tcg_env, cpu_gpr[a->rb]);
#else
qemu_build_not_reached();
#endif
diff --git a/target/ppc/translate/spe-impl.c.inc b/target/ppc/translate/spe-impl.c.inc
index f4a8584..454dac8 100644
--- a/target/ppc/translate/spe-impl.c.inc
+++ b/target/ppc/translate/spe-impl.c.inc
@@ -22,7 +22,7 @@ static inline void gen_evmra(DisasContext *ctx)
cpu_gprh[rA(ctx->opcode)]);
/* spe_acc := tmp */
- tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
+ tcg_gen_st_i64(tmp, tcg_env, offsetof(CPUPPCState, spe_acc));
/* rD := rA */
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
@@ -457,7 +457,7 @@ static inline void gen_evmwumia(DisasContext *ctx)
/* acc := rD */
gen_load_gpr64(tmp, rD(ctx->opcode));
- tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
+ tcg_gen_st_i64(tmp, tcg_env, offsetof(CPUPPCState, spe_acc));
}
static inline void gen_evmwumiaa(DisasContext *ctx)
@@ -479,13 +479,13 @@ static inline void gen_evmwumiaa(DisasContext *ctx)
gen_load_gpr64(tmp, rD(ctx->opcode));
/* Load acc */
- tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
+ tcg_gen_ld_i64(acc, tcg_env, offsetof(CPUPPCState, spe_acc));
/* acc := tmp + acc */
tcg_gen_add_i64(acc, acc, tmp);
/* Store acc */
- tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
+ tcg_gen_st_i64(acc, tcg_env, offsetof(CPUPPCState, spe_acc));
/* rD := acc */
gen_store_gpr64(rD(ctx->opcode), acc);
@@ -529,7 +529,7 @@ static inline void gen_evmwsmia(DisasContext *ctx)
/* acc := rD */
gen_load_gpr64(tmp, rD(ctx->opcode));
- tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
+ tcg_gen_st_i64(tmp, tcg_env, offsetof(CPUPPCState, spe_acc));
}
static inline void gen_evmwsmiaa(DisasContext *ctx)
@@ -551,13 +551,13 @@ static inline void gen_evmwsmiaa(DisasContext *ctx)
gen_load_gpr64(tmp, rD(ctx->opcode));
/* Load acc */
- tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
+ tcg_gen_ld_i64(acc, tcg_env, offsetof(CPUPPCState, spe_acc));
/* acc := tmp + acc */
tcg_gen_add_i64(acc, acc, tmp);
/* Store acc */
- tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
+ tcg_gen_st_i64(acc, tcg_env, offsetof(CPUPPCState, spe_acc));
/* rD := acc */
gen_store_gpr64(rD(ctx->opcode), acc);
@@ -878,7 +878,7 @@ static inline void gen_##name(DisasContext *ctx) \
{ \
TCGv_i32 t0 = tcg_temp_new_i32(); \
tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
- gen_helper_##name(t0, cpu_env, t0); \
+ gen_helper_##name(t0, tcg_env, t0); \
tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
}
#define GEN_SPEFPUOP_CONV_32_64(name) \
@@ -893,7 +893,7 @@ static inline void gen_##name(DisasContext *ctx) \
t0 = tcg_temp_new_i64(); \
t1 = tcg_temp_new_i32(); \
gen_load_gpr64(t0, rB(ctx->opcode)); \
- gen_helper_##name(t1, cpu_env, t0); \
+ gen_helper_##name(t1, tcg_env, t0); \
tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \
}
#define GEN_SPEFPUOP_CONV_64_32(name) \
@@ -908,7 +908,7 @@ static inline void gen_##name(DisasContext *ctx) \
t0 = tcg_temp_new_i64(); \
t1 = tcg_temp_new_i32(); \
tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
- gen_helper_##name(t0, cpu_env, t1); \
+ gen_helper_##name(t0, tcg_env, t1); \
gen_store_gpr64(rD(ctx->opcode), t0); \
}
#define GEN_SPEFPUOP_CONV_64_64(name) \
@@ -921,7 +921,7 @@ static inline void gen_##name(DisasContext *ctx) \
} \
t0 = tcg_temp_new_i64(); \
gen_load_gpr64(t0, rB(ctx->opcode)); \
- gen_helper_##name(t0, cpu_env, t0); \
+ gen_helper_##name(t0, tcg_env, t0); \
gen_store_gpr64(rD(ctx->opcode), t0); \
}
#define GEN_SPEFPUOP_ARITH2_32_32(name) \
@@ -931,7 +931,7 @@ static inline void gen_##name(DisasContext *ctx) \
TCGv_i32 t1 = tcg_temp_new_i32(); \
tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
- gen_helper_##name(t0, cpu_env, t0, t1); \
+ gen_helper_##name(t0, tcg_env, t0, t1); \
tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
}
#define GEN_SPEFPUOP_ARITH2_64_64(name) \
@@ -946,7 +946,7 @@ static inline void gen_##name(DisasContext *ctx) \
t1 = tcg_temp_new_i64(); \
gen_load_gpr64(t0, rA(ctx->opcode)); \
gen_load_gpr64(t1, rB(ctx->opcode)); \
- gen_helper_##name(t0, cpu_env, t0, t1); \
+ gen_helper_##name(t0, tcg_env, t0, t1); \
gen_store_gpr64(rD(ctx->opcode), t0); \
}
#define GEN_SPEFPUOP_COMP_32(name) \
@@ -957,7 +957,7 @@ static inline void gen_##name(DisasContext *ctx) \
\
tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
- gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
+ gen_helper_##name(cpu_crf[crfD(ctx->opcode)], tcg_env, t0, t1); \
}
#define GEN_SPEFPUOP_COMP_64(name) \
static inline void gen_##name(DisasContext *ctx) \
@@ -971,7 +971,7 @@ static inline void gen_##name(DisasContext *ctx) \
t1 = tcg_temp_new_i64(); \
gen_load_gpr64(t0, rA(ctx->opcode)); \
gen_load_gpr64(t1, rB(ctx->opcode)); \
- gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
+ gen_helper_##name(cpu_crf[crfD(ctx->opcode)], tcg_env, t0, t1); \
}
/* Single precision floating-point vectors operations */
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc b/target/ppc/translate/storage-ctrl-impl.c.inc
index faa7b04..74c23a4 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -30,7 +30,7 @@ static bool trans_SLBIE(DisasContext *ctx, arg_SLBIE *a)
REQUIRE_SV(ctx);
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
- gen_helper_SLBIE(cpu_env, cpu_gpr[a->rb]);
+ gen_helper_SLBIE(tcg_env, cpu_gpr[a->rb]);
#else
qemu_build_not_reached();
#endif
@@ -44,7 +44,7 @@ static bool trans_SLBIEG(DisasContext *ctx, arg_SLBIEG *a)
REQUIRE_SV(ctx);
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
- gen_helper_SLBIEG(cpu_env, cpu_gpr[a->rb]);
+ gen_helper_SLBIEG(tcg_env, cpu_gpr[a->rb]);
#else
qemu_build_not_reached();
#endif
@@ -58,7 +58,7 @@ static bool trans_SLBIA(DisasContext *ctx, arg_SLBIA *a)
REQUIRE_SV(ctx);
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
- gen_helper_SLBIA(cpu_env, tcg_constant_i32(a->ih));
+ gen_helper_SLBIA(tcg_env, tcg_constant_i32(a->ih));
#else
qemu_build_not_reached();
#endif
@@ -72,7 +72,7 @@ static bool trans_SLBIAG(DisasContext *ctx, arg_SLBIAG *a)
REQUIRE_SV(ctx);
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
- gen_helper_SLBIAG(cpu_env, cpu_gpr[a->rs], tcg_constant_i32(a->l));
+ gen_helper_SLBIAG(tcg_env, cpu_gpr[a->rs], tcg_constant_i32(a->l));
#else
qemu_build_not_reached();
#endif
@@ -86,7 +86,7 @@ static bool trans_SLBMTE(DisasContext *ctx, arg_SLBMTE *a)
REQUIRE_SV(ctx);
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
- gen_helper_SLBMTE(cpu_env, cpu_gpr[a->rb], cpu_gpr[a->rt]);
+ gen_helper_SLBMTE(tcg_env, cpu_gpr[a->rb], cpu_gpr[a->rt]);
#else
qemu_build_not_reached();
#endif
@@ -100,7 +100,7 @@ static bool trans_SLBMFEV(DisasContext *ctx, arg_SLBMFEV *a)
REQUIRE_SV(ctx);
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
- gen_helper_SLBMFEV(cpu_gpr[a->rt], cpu_env, cpu_gpr[a->rb]);
+ gen_helper_SLBMFEV(cpu_gpr[a->rt], tcg_env, cpu_gpr[a->rb]);
#else
qemu_build_not_reached();
#endif
@@ -114,7 +114,7 @@ static bool trans_SLBMFEE(DisasContext *ctx, arg_SLBMFEE *a)
REQUIRE_SV(ctx);
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
- gen_helper_SLBMFEE(cpu_gpr[a->rt], cpu_env, cpu_gpr[a->rb]);
+ gen_helper_SLBMFEE(cpu_gpr[a->rt], tcg_env, cpu_gpr[a->rb]);
#else
qemu_build_not_reached();
#endif
@@ -137,7 +137,7 @@ static bool trans_SLBFEE(DisasContext *ctx, arg_SLBFEE *a)
gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
return true;
}
- gen_helper_SLBFEE(cpu_gpr[a->rt], cpu_env,
+ gen_helper_SLBFEE(cpu_gpr[a->rt], tcg_env,
cpu_gpr[a->rb]);
l1 = gen_new_label();
l2 = gen_new_label();
@@ -211,7 +211,7 @@ static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
if (!local && NARROW_MODE(ctx)) {
TCGv t0 = tcg_temp_new();
tcg_gen_ext32u_tl(t0, cpu_gpr[rb]);
- gen_helper_tlbie(cpu_env, t0);
+ gen_helper_tlbie(tcg_env, t0);
#if defined(TARGET_PPC64)
/*
@@ -219,7 +219,7 @@ static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
* otherwise the results are undefined.
*/
} else if (a->r) {
- gen_helper_tlbie_isa300(cpu_env, cpu_gpr[rb], cpu_gpr[a->rs],
+ gen_helper_tlbie_isa300(tcg_env, cpu_gpr[rb], cpu_gpr[a->rs],
tcg_constant_i32(a->ric << TLBIE_F_RIC_SHIFT |
a->prs << TLBIE_F_PRS_SHIFT |
a->r << TLBIE_F_R_SHIFT |
@@ -228,7 +228,7 @@ static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
#endif
} else {
- gen_helper_tlbie(cpu_env, cpu_gpr[rb]);
+ gen_helper_tlbie(tcg_env, cpu_gpr[rb]);
}
if (local) {
@@ -236,9 +236,9 @@ static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
}
t1 = tcg_temp_new_i32();
- tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
+ tcg_gen_ld_i32(t1, tcg_env, offsetof(CPUPPCState, tlb_need_flush));
tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH);
- tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
+ tcg_gen_st_i32(t1, tcg_env, offsetof(CPUPPCState, tlb_need_flush));
return true;
#endif
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 5cdf53a..4b91c34 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -10,7 +10,7 @@
static inline TCGv_ptr gen_avr_ptr(int reg)
{
TCGv_ptr r = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(r, cpu_env, avr_full_offset(reg));
+ tcg_gen_addi_ptr(r, tcg_env, avr_full_offset(reg));
return r;
}
@@ -96,7 +96,7 @@ static void gen_lve##name(DisasContext *ctx) \
tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
} \
rs = gen_avr_ptr(rS(ctx->opcode)); \
- gen_helper_lve##name(cpu_env, rs, EA); \
+ gen_helper_lve##name(tcg_env, rs, EA); \
}
#define GEN_VR_STVE(name, opc2, opc3, size) \
@@ -115,7 +115,7 @@ static void gen_stve##name(DisasContext *ctx) \
tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
} \
rs = gen_avr_ptr(rS(ctx->opcode)); \
- gen_helper_stve##name(cpu_env, rs, EA); \
+ gen_helper_stve##name(tcg_env, rs, EA); \
}
GEN_VR_LDX(lvx, 0x07, 0x03);
@@ -146,7 +146,7 @@ static void gen_mfvscr(DisasContext *ctx)
tcg_gen_movi_i64(avr, 0);
set_avr64(rD(ctx->opcode), avr, true);
t = tcg_temp_new_i32();
- gen_helper_mfvscr(t, cpu_env);
+ gen_helper_mfvscr(t, tcg_env);
tcg_gen_extu_i32_i64(avr, t);
set_avr64(rD(ctx->opcode), avr, false);
}
@@ -167,8 +167,8 @@ static void gen_mtvscr(DisasContext *ctx)
bofs += 3 * 4;
#endif
- tcg_gen_ld_i32(val, cpu_env, bofs);
- gen_helper_mtvscr(cpu_env, val);
+ tcg_gen_ld_i32(val, tcg_env, bofs);
+ gen_helper_mtvscr(tcg_env, val);
}
static void gen_vx_vmul10(DisasContext *ctx, bool add_cin, bool ret_carry)
@@ -287,7 +287,7 @@ static void glue(gen_, name)(DisasContext *ctx) \
ra = gen_avr_ptr(rA(ctx->opcode)); \
rb = gen_avr_ptr(rB(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \
- gen_helper_##name(cpu_env, rd, ra, rb); \
+ gen_helper_##name(tcg_env, rd, ra, rb); \
}
#define GEN_VXFORM3(name, opc2, opc3) \
@@ -689,10 +689,10 @@ static void trans_vclzw(DisasContext *ctx)
/* Perform count for every word element using tcg_gen_clzi_i32. */
for (i = 0; i < 4; i++) {
- tcg_gen_ld_i32(tmp, cpu_env,
+ tcg_gen_ld_i32(tmp, tcg_env,
offsetof(CPUPPCState, vsr[32 + VB].u64[0]) + i * 4);
tcg_gen_clzi_i32(tmp, tmp, 32);
- tcg_gen_st_i32(tmp, cpu_env,
+ tcg_gen_st_i32(tmp, tcg_env,
offsetof(CPUPPCState, vsr[32 + VT].u64[0]) + i * 4);
}
}
@@ -1174,7 +1174,7 @@ static void glue(gen_, name)(DisasContext *ctx) \
ra = gen_avr_ptr(rA(ctx->opcode)); \
rb = gen_avr_ptr(rB(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \
- gen_helper_##opname(cpu_env, rd, ra, rb); \
+ gen_helper_##opname(tcg_env, rd, ra, rb); \
}
#define GEN_VXRFORM(name, opc2, opc3) \
@@ -1478,7 +1478,7 @@ static void glue(gen_, name)(DisasContext *ctx) \
} \
rb = gen_avr_ptr(rB(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \
- gen_helper_##name(cpu_env, rd, rb); \
+ gen_helper_##name(tcg_env, rd, rb); \
}
#define GEN_VXFORM_NOA_2(name, opc2, opc3, opc4) \
@@ -1625,7 +1625,7 @@ static void glue(gen_, name)(DisasContext *ctx) \
uimm = tcg_constant_i32(UIMM5(ctx->opcode)); \
rb = gen_avr_ptr(rB(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \
- gen_helper_##name(cpu_env, rd, rb, uimm); \
+ gen_helper_##name(tcg_env, rd, rb, uimm); \
}
#define GEN_VXFORM_UIMM_SPLAT(name, opc2, opc3, splat_max) \
@@ -1813,7 +1813,7 @@ static bool do_vextdx(DisasContext *ctx, arg_VA *a, int size, bool right,
if (right) {
tcg_gen_subfi_tl(rc, 32 - size, rc);
}
- gen_helper(cpu_env, vrt, vra, vrb, rc);
+ gen_helper(tcg_env, vrt, vra, vrb, rc);
return true;
}
@@ -1841,7 +1841,7 @@ static bool do_vinsx(DisasContext *ctx, int vrt, int size, bool right, TCGv ra,
tcg_gen_subfi_tl(idx, 16 - size, idx);
}
- gen_helper(cpu_env, t, rb, idx);
+ gen_helper(tcg_env, t, rb, idx);
return true;
}
@@ -2349,9 +2349,9 @@ static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
rc = gen_avr_ptr(rC(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \
if (Rc(ctx->opcode)) { \
- gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
+ gen_helper_##name1(tcg_env, rd, ra, rb, rc); \
} else { \
- gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
+ gen_helper_##name0(tcg_env, rd, ra, rb, rc); \
} \
}
@@ -2437,7 +2437,7 @@ static bool do_va_env_helper(DisasContext *ctx, arg_VA *a,
vra = gen_avr_ptr(a->vra);
vrb = gen_avr_ptr(a->vrb);
vrc = gen_avr_ptr(a->rc);
- gen_helper(cpu_env, vrt, vra, vrb, vrc);
+ gen_helper(tcg_env, vrt, vra, vrb, vrc);
return true;
}
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 0f5b005..6db87ab 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -2,25 +2,25 @@
static inline void get_cpu_vsr(TCGv_i64 dst, int n, bool high)
{
- tcg_gen_ld_i64(dst, cpu_env, vsr64_offset(n, high));
+ tcg_gen_ld_i64(dst, tcg_env, vsr64_offset(n, high));
}
static inline void set_cpu_vsr(int n, TCGv_i64 src, bool high)
{
- tcg_gen_st_i64(src, cpu_env, vsr64_offset(n, high));
+ tcg_gen_st_i64(src, tcg_env, vsr64_offset(n, high));
}
static inline TCGv_ptr gen_vsr_ptr(int reg)
{
TCGv_ptr r = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(r, cpu_env, vsr_full_offset(reg));
+ tcg_gen_addi_ptr(r, tcg_env, vsr_full_offset(reg));
return r;
}
static inline TCGv_ptr gen_acc_ptr(int reg)
{
TCGv_ptr r = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(r, cpu_env, acc_full_offset(reg));
+ tcg_gen_addi_ptr(r, tcg_env, acc_full_offset(reg));
return r;
}
@@ -257,7 +257,7 @@ static void gen_##name(DisasContext *ctx) \
xt = gen_vsr_ptr(xT(ctx->opcode)); \
gen_set_access_type(ctx, ACCESS_INT); \
gen_addr_register(ctx, EA); \
- gen_helper_##name(cpu_env, EA, xt, cpu_gpr[rB(ctx->opcode)]); \
+ gen_helper_##name(tcg_env, EA, xt, cpu_gpr[rB(ctx->opcode)]); \
}
VSX_VECTOR_LOAD_STORE_LENGTH(lxvl)
@@ -801,10 +801,10 @@ static void gen_##name(DisasContext *ctx) \
xa = gen_vsr_ptr(xA(ctx->opcode)); \
xb = gen_vsr_ptr(xB(ctx->opcode)); \
if ((ctx->opcode >> (31 - 21)) & 1) { \
- gen_helper_##name(cpu_crf[6], cpu_env, xt, xa, xb); \
+ gen_helper_##name(cpu_crf[6], tcg_env, xt, xa, xb); \
} else { \
ignored = tcg_temp_new_i32(); \
- gen_helper_##name(ignored, cpu_env, xt, xa, xb); \
+ gen_helper_##name(ignored, tcg_env, xt, xa, xb); \
} \
}
@@ -829,7 +829,7 @@ static bool trans_XSCVQPDP(DisasContext *ctx, arg_X_tb_rc *a)
xt = gen_avr_ptr(a->rt);
xb = gen_avr_ptr(a->rb);
- gen_helper_XSCVQPDP(cpu_env, ro, xt, xb);
+ gen_helper_XSCVQPDP(tcg_env, ro, xt, xb);
return true;
}
@@ -843,7 +843,7 @@ static bool do_helper_env_X_tb(DisasContext *ctx, arg_X_tb *a,
xt = gen_avr_ptr(a->rt);
xb = gen_avr_ptr(a->rb);
- gen_helper(cpu_env, xt, xb);
+ gen_helper(tcg_env, xt, xb);
return true;
}
@@ -861,7 +861,7 @@ static void gen_##name(DisasContext *ctx) \
return; \
} \
opc = tcg_constant_i32(ctx->opcode); \
- gen_helper_##name(cpu_env, opc); \
+ gen_helper_##name(tcg_env, opc); \
}
#define GEN_VSX_HELPER_X3(name, op1, op2, inval, type) \
@@ -875,7 +875,7 @@ static void gen_##name(DisasContext *ctx) \
xt = gen_vsr_ptr(xT(ctx->opcode)); \
xa = gen_vsr_ptr(xA(ctx->opcode)); \
xb = gen_vsr_ptr(xB(ctx->opcode)); \
- gen_helper_##name(cpu_env, xt, xa, xb); \
+ gen_helper_##name(tcg_env, xt, xa, xb); \
}
#define GEN_VSX_HELPER_X2(name, op1, op2, inval, type) \
@@ -888,7 +888,7 @@ static void gen_##name(DisasContext *ctx) \
} \
xt = gen_vsr_ptr(xT(ctx->opcode)); \
xb = gen_vsr_ptr(xB(ctx->opcode)); \
- gen_helper_##name(cpu_env, xt, xb); \
+ gen_helper_##name(tcg_env, xt, xb); \
}
#define GEN_VSX_HELPER_X2_AB(name, op1, op2, inval, type) \
@@ -903,7 +903,7 @@ static void gen_##name(DisasContext *ctx) \
opc = tcg_constant_i32(ctx->opcode); \
xa = gen_vsr_ptr(xA(ctx->opcode)); \
xb = gen_vsr_ptr(xB(ctx->opcode)); \
- gen_helper_##name(cpu_env, opc, xa, xb); \
+ gen_helper_##name(tcg_env, opc, xa, xb); \
}
#define GEN_VSX_HELPER_X1(name, op1, op2, inval, type) \
@@ -917,7 +917,7 @@ static void gen_##name(DisasContext *ctx) \
} \
opc = tcg_constant_i32(ctx->opcode); \
xb = gen_vsr_ptr(xB(ctx->opcode)); \
- gen_helper_##name(cpu_env, opc, xb); \
+ gen_helper_##name(tcg_env, opc, xb); \
}
#define GEN_VSX_HELPER_R3(name, op1, op2, inval, type) \
@@ -933,7 +933,7 @@ static void gen_##name(DisasContext *ctx) \
xt = gen_vsr_ptr(rD(ctx->opcode) + 32); \
xa = gen_vsr_ptr(rA(ctx->opcode) + 32); \
xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \
- gen_helper_##name(cpu_env, opc, xt, xa, xb); \
+ gen_helper_##name(tcg_env, opc, xt, xa, xb); \
}
#define GEN_VSX_HELPER_R2(name, op1, op2, inval, type) \
@@ -948,7 +948,7 @@ static void gen_##name(DisasContext *ctx) \
opc = tcg_constant_i32(ctx->opcode); \
xt = gen_vsr_ptr(rD(ctx->opcode) + 32); \
xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \
- gen_helper_##name(cpu_env, opc, xt, xb); \
+ gen_helper_##name(tcg_env, opc, xt, xb); \
}
#define GEN_VSX_HELPER_R2_AB(name, op1, op2, inval, type) \
@@ -963,7 +963,7 @@ static void gen_##name(DisasContext *ctx) \
opc = tcg_constant_i32(ctx->opcode); \
xa = gen_vsr_ptr(rA(ctx->opcode) + 32); \
xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \
- gen_helper_##name(cpu_env, opc, xa, xb); \
+ gen_helper_##name(tcg_env, opc, xa, xb); \
}
#define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
@@ -978,7 +978,7 @@ static void gen_##name(DisasContext *ctx) \
t0 = tcg_temp_new_i64(); \
t1 = tcg_temp_new_i64(); \
get_cpu_vsr(t0, xB(ctx->opcode), true); \
- gen_helper_##name(t1, cpu_env, t0); \
+ gen_helper_##name(t1, tcg_env, t0); \
set_cpu_vsr(xT(ctx->opcode), t1, true); \
set_cpu_vsr(xT(ctx->opcode), tcg_constant_i64(0), false); \
}
@@ -1191,7 +1191,7 @@ static bool do_XX2_bf_uim(DisasContext *ctx, arg_XX2_bf_uim *a, bool vsr,
REQUIRE_VSX(ctx);
xb = vsr ? gen_vsr_ptr(a->xb) : gen_avr_ptr(a->xb);
- gen_helper(cpu_env, tcg_constant_i32(a->bf), tcg_constant_i32(a->uim), xb);
+ gen_helper(tcg_env, tcg_constant_i32(a->bf), tcg_constant_i32(a->uim), xb);
return true;
}
@@ -1420,7 +1420,7 @@ static bool do_xsmadd(DisasContext *ctx, int tgt, int src1, int src2, int src3,
s2 = gen_vsr_ptr(src2);
s3 = gen_vsr_ptr(src3);
- gen_helper(cpu_env, t, s1, s2, s3);
+ gen_helper(tcg_env, t, s1, s2, s3);
return true;
}
@@ -1500,7 +1500,7 @@ static void gen_##name(DisasContext *ctx) \
s2 = gen_vsr_ptr(xT(ctx->opcode)); \
s3 = gen_vsr_ptr(xB(ctx->opcode)); \
} \
- gen_helper_##name(cpu_env, xt, s1, s2, s3); \
+ gen_helper_##name(tcg_env, xt, s1, s2, s3); \
}
GEN_VSX_HELPER_VSX_MADD(xvmadddp, 0x04, 0x0C, 0x0D, 0, PPC2_VSX)
@@ -1728,9 +1728,9 @@ static bool trans_XXSPLTI32DX(DisasContext *ctx, arg_8RR_D_IX *a)
imm = tcg_constant_i32(a->si);
- tcg_gen_st_i32(imm, cpu_env,
+ tcg_gen_st_i32(imm, tcg_env,
offsetof(CPUPPCState, vsr[a->xt].VsrW(0 + a->ix)));
- tcg_gen_st_i32(imm, cpu_env,
+ tcg_gen_st_i32(imm, tcg_env,
offsetof(CPUPPCState, vsr[a->xt].VsrW(2 + a->ix)));
return true;
@@ -2720,7 +2720,7 @@ static bool do_helper_XX3(DisasContext *ctx, arg_XX3 *a,
xa = gen_vsr_ptr(a->xa);
xb = gen_vsr_ptr(a->xb);
- helper(cpu_env, xt, xa, xb);
+ helper(tcg_env, xt, xa, xb);
return true;
}
@@ -2741,7 +2741,7 @@ static bool do_helper_X(arg_X *a,
ra = gen_avr_ptr(a->ra);
rb = gen_avr_ptr(a->rb);
- helper(cpu_env, rt, ra, rb);
+ helper(tcg_env, rt, ra, rb);
return true;
}
@@ -2770,7 +2770,7 @@ static bool trans_XVCVSPBF16(DisasContext *ctx, arg_XX2 *a)
xt = gen_vsr_ptr(a->xt);
xb = gen_vsr_ptr(a->xb);
- gen_helper_XVCVSPBF16(cpu_env, xt, xb);
+ gen_helper_XVCVSPBF16(tcg_env, xt, xb);
return true;
}
@@ -2833,7 +2833,7 @@ static bool do_ger(DisasContext *ctx, arg_MMIRR_XX3 *a,
xb = gen_vsr_ptr(a->xb);
mask = ger_pack_masks(a->pmsk, a->ymsk, a->xmsk);
- helper(cpu_env, xa, xb, xt, tcg_constant_i32(mask));
+ helper(tcg_env, xa, xb, xt, tcg_constant_i32(mask));
return true;
}
generated by cgit v1.1 at 2025-01-11 10:47:23 +0000