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-rw-r--r--target/mips/cpu.h4
1 files changed, 0 insertions, 4 deletions
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index f10e016..eccee37 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -876,10 +876,8 @@ struct CPUMIPSState {
*/
target_ulong lladdr; /* LL virtual address compared against SC */
target_ulong llval;
- target_ulong llnewval;
uint64_t llval_wp;
uint32_t llnewval_wp;
- target_ulong llreg;
uint64_t CP0_LLAddr_rw_bitmask;
int CP0_LLAddr_shift;
/*
@@ -1156,8 +1154,6 @@ enum {
EXCP_LAST = EXCP_TLBRI,
};
-/* Dummy exception for conditional stores. */
-#define EXCP_SC 0x100
/*
* This is an internally generated WAKE request line.