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-rw-r--r--target/arm/cpu_tcg.c7
1 files changed, 2 insertions, 5 deletions
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index ed444bf..33cc75a 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -654,12 +654,9 @@ static void cortex_m55_initfn(Object *obj)
cpu->revidr = 0;
cpu->pmsav7_dregion = 16;
cpu->sau_sregion = 8;
- /*
- * These are the MVFR* values for the FPU, no MVE configuration;
- * we will update them later when we implement MVE
- */
+ /* These are the MVFR* values for the FPU + full MVE configuration */
cpu->isar.mvfr0 = 0x10110221;
- cpu->isar.mvfr1 = 0x12100011;
+ cpu->isar.mvfr1 = 0x12100211;
cpu->isar.mvfr2 = 0x00000040;
cpu->isar.id_pfr0 = 0x20000030;
cpu->isar.id_pfr1 = 0x00000230;