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-rw-r--r--target-ppc/exec.h4
-rw-r--r--target-ppc/op.c14
-rw-r--r--target-ppc/op_helper.c22
-rw-r--r--target-ppc/op_helper.h6
4 files changed, 25 insertions, 21 deletions
diff --git a/target-ppc/exec.h b/target-ppc/exec.h
index f14f6a8..76fdb0b 100644
--- a/target-ppc/exec.h
+++ b/target-ppc/exec.h
@@ -27,6 +27,10 @@
#include "cpu.h"
#include "exec-all.h"
+/* For normal operations, precise emulation should not be needed */
+//#define USE_PRECISE_EMULATION 1
+#define USE_PRECISE_EMULATION 0
+
register struct CPUPPCState *env asm(AREG0);
#if TARGET_LONG_BITS > HOST_LONG_BITS
/* no registers can be used */
diff --git a/target-ppc/op.c b/target-ppc/op.c
index f60a6a9..972b8bc 100644
--- a/target-ppc/op.c
+++ b/target-ppc/op.c
@@ -1716,7 +1716,7 @@ void OPPROTO op_srli_T1_64 (void)
/* fadd - fadd. */
void OPPROTO op_fadd (void)
{
-#ifdef CONFIG_SOFTFLOAT
+#if USE_PRECISE_EMULATION
do_fadd();
#else
FT0 = float64_add(FT0, FT1, &env->fp_status);
@@ -1727,7 +1727,7 @@ void OPPROTO op_fadd (void)
/* fsub - fsub. */
void OPPROTO op_fsub (void)
{
-#ifdef CONFIG_SOFTFLOAT
+#if USE_PRECISE_EMULATION
do_fsub();
#else
FT0 = float64_sub(FT0, FT1, &env->fp_status);
@@ -1738,7 +1738,7 @@ void OPPROTO op_fsub (void)
/* fmul - fmul. */
void OPPROTO op_fmul (void)
{
-#ifdef CONFIG_SOFTFLOAT
+#if USE_PRECISE_EMULATION
do_fmul();
#else
FT0 = float64_mul(FT0, FT1, &env->fp_status);
@@ -1749,7 +1749,7 @@ void OPPROTO op_fmul (void)
/* fdiv - fdiv. */
void OPPROTO op_fdiv (void)
{
-#ifdef CONFIG_SOFTFLOAT
+#if USE_PRECISE_EMULATION
do_fdiv();
#else
FT0 = float64_div(FT0, FT1, &env->fp_status);
@@ -1796,7 +1796,7 @@ void OPPROTO op_fsel (void)
/* fmadd - fmadd. */
void OPPROTO op_fmadd (void)
{
-#ifdef CONFIG_SOFTFLOAT
+#if USE_PRECISE_EMULATION
do_fmadd();
#else
FT0 = float64_mul(FT0, FT1, &env->fp_status);
@@ -1808,7 +1808,7 @@ void OPPROTO op_fmadd (void)
/* fmsub - fmsub. */
void OPPROTO op_fmsub (void)
{
-#ifdef CONFIG_SOFTFLOAT
+#if USE_PRECISE_EMULATION
do_fmsub();
#else
FT0 = float64_mul(FT0, FT1, &env->fp_status);
@@ -1835,7 +1835,7 @@ void OPPROTO op_fnmsub (void)
/* frsp - frsp. */
void OPPROTO op_frsp (void)
{
-#ifdef CONFIG_SOFTFLOAT
+#if USE_PRECISE_EMULATION
do_frsp();
#else
FT0 = float64_to_float32(FT0, &env->fp_status);
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 919b481..544d906 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -922,7 +922,7 @@ void do_float_check_status (void)
}
#endif
-#ifdef CONFIG_SOFTFLOAT
+#if USE_PRECISE_EMULATION
void do_fadd (void)
{
if (unlikely(float64_is_signaling_nan(FT0) ||
@@ -989,7 +989,7 @@ void do_fdiv (void)
FT0 = float64_div(FT0, FT1, &env->fp_status);
}
}
-#endif /* CONFIG_SOFTFLOAT */
+#endif /* USE_PRECISE_EMULATION */
void do_fctiw (void)
{
@@ -1003,7 +1003,7 @@ void do_fctiw (void)
fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
} else {
p.ll = float64_to_int32(FT0, &env->fp_status);
-#ifdef CONFIG_SOFTFLOAT
+#if USE_PRECISE_EMULATION
/* XXX: higher bits are not supposed to be significant.
* to make tests easier, return the same as a real PowerPC 750
*/
@@ -1025,7 +1025,7 @@ void do_fctiwz (void)
fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
} else {
p.ll = float64_to_int32_round_to_zero(FT0, &env->fp_status);
-#ifdef CONFIG_SOFTFLOAT
+#if USE_PRECISE_EMULATION
/* XXX: higher bits are not supposed to be significant.
* to make tests easier, return the same as a real PowerPC 750
*/
@@ -1114,7 +1114,7 @@ void do_frim (void)
do_fri(float_round_down);
}
-#ifdef CONFIG_SOFTFLOAT
+#if USE_PRECISE_EMULATION
void do_fmadd (void)
{
if (unlikely(float64_is_signaling_nan(FT0) ||
@@ -1164,7 +1164,7 @@ void do_fmsub (void)
#endif
}
}
-#endif /* CONFIG_SOFTFLOAT */
+#endif /* USE_PRECISE_EMULATION */
void do_fnmadd (void)
{
@@ -1174,7 +1174,7 @@ void do_fnmadd (void)
/* sNaN operation */
fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
} else {
-#ifdef CONFIG_SOFTFLOAT
+#if USE_PRECISE_EMULATION
#ifdef FLOAT128
/* This is the way the PowerPC specification defines it */
float128 ft0_128, ft1_128;
@@ -1206,7 +1206,7 @@ void do_fnmsub (void)
/* sNaN operation */
fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
} else {
-#ifdef CONFIG_SOFTFLOAT
+#if USE_PRECISE_EMULATION
#ifdef FLOAT128
/* This is the way the PowerPC specification defines it */
float128 ft0_128, ft1_128;
@@ -1230,7 +1230,7 @@ void do_fnmsub (void)
}
}
-#ifdef CONFIG_SOFTFLOAT
+#if USE_PRECISE_EMULATION
void do_frsp (void)
{
if (unlikely(float64_is_signaling_nan(FT0))) {
@@ -1240,7 +1240,7 @@ void do_frsp (void)
FT0 = float64_to_float32(FT0, &env->fp_status);
}
}
-#endif /* CONFIG_SOFTFLOAT */
+#endif /* USE_PRECISE_EMULATION */
void do_fsqrt (void)
{
@@ -1295,7 +1295,7 @@ void do_fres (void)
/* Zero reciprocal */
float_zero_divide_excp();
} else if (likely(isnormal(FT0))) {
-#ifdef CONFIG_SOFTFLOAT
+#if USE_PRECISE_EMULATION
FT0 = float64_div(1.0, FT0, &env->fp_status);
FT0 = float64_to_float32(FT0, &env->fp_status);
#else
diff --git a/target-ppc/op_helper.h b/target-ppc/op_helper.h
index 0510f0a..1d5fc0a 100644
--- a/target-ppc/op_helper.h
+++ b/target-ppc/op_helper.h
@@ -98,7 +98,7 @@ void do_compute_fprf (int set_class);
#ifdef CONFIG_SOFTFLOAT
void do_float_check_status (void);
#endif
-#ifdef CONFIG_SOFTFLOAT
+#if USE_PRECISE_EMULATION
void do_fadd (void);
void do_fsub (void);
void do_fmul (void);
@@ -109,13 +109,13 @@ void do_fre (void);
void do_fres (void);
void do_frsqrte (void);
void do_fsel (void);
-#ifdef CONFIG_SOFTFLOAT
+#if USE_PRECISE_EMULATION
void do_fmadd (void);
void do_fmsub (void);
#endif
void do_fnmadd (void);
void do_fnmsub (void);
-#ifdef CONFIG_SOFTFLOAT
+#if USE_PRECISE_EMULATION
void do_frsp (void);
#endif
void do_fctiw (void);
generated by cgit v1.1 at 2024-12-26 06:19:54 +0000