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-rw-r--r--target-ppc/translate.c18
1 files changed, 18 insertions, 0 deletions
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index f00b606..30dba74 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7019,6 +7019,22 @@ static void gen_lxvd2x(DisasContext *ctx)
tcg_temp_free(EA);
}
+static void gen_stxvd2x(DisasContext *ctx)
+{
+ TCGv EA;
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ gen_set_access_type(ctx, ACCESS_INT);
+ EA = tcg_temp_new();
+ gen_addr_reg_index(ctx, EA);
+ gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
+ tcg_gen_addi_tl(EA, EA, 8);
+ gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
+ tcg_temp_free(EA);
+}
+
/*** SPE extension ***/
/* Register moves */
@@ -9470,6 +9486,8 @@ GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
+GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
+
#undef GEN_SPE
#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)