diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/riscv/sifive_u.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index a9f7b4a..8824b7c 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -26,6 +26,7 @@ #include "hw/gpio/sifive_gpio.h" #include "hw/misc/sifive_u_otp.h" #include "hw/misc/sifive_u_prci.h" +#include "hw/ssi/sifive_spi.h" #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc" #define RISCV_U_SOC(obj) \ @@ -45,6 +46,7 @@ typedef struct SiFiveUSoCState { SIFIVEGPIOState gpio; SiFiveUOTPState otp; SiFivePDMAState dma; + SiFiveSPIState spi0; CadenceGEMState gem; uint32_t serial; @@ -82,6 +84,7 @@ enum { SIFIVE_U_DEV_UART0, SIFIVE_U_DEV_UART1, SIFIVE_U_DEV_GPIO, + SIFIVE_U_DEV_QSPI0, SIFIVE_U_DEV_OTP, SIFIVE_U_DEV_DMC, SIFIVE_U_DEV_FLASH0, @@ -120,6 +123,7 @@ enum { SIFIVE_U_PDMA_IRQ5 = 28, SIFIVE_U_PDMA_IRQ6 = 29, SIFIVE_U_PDMA_IRQ7 = 30, + SIFIVE_U_QSPI0_IRQ = 51, SIFIVE_U_GEM_IRQ = 0x35 }; |