diff options
Diffstat (limited to 'include/hw/riscv')
| -rw-r--r-- | include/hw/riscv/boot.h | 14 | ||||
| -rw-r--r-- | include/hw/riscv/microchip_pfsoc.h | 3 | ||||
| -rw-r--r-- | include/hw/riscv/opentitan.h | 23 | ||||
| -rw-r--r-- | include/hw/riscv/spike.h | 6 | ||||
| -rw-r--r-- | include/hw/riscv/virt.h | 6 |
5 files changed, 29 insertions, 23 deletions
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 0b01988..20ff5fe 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -22,10 +22,11 @@ #include "exec/cpu-defs.h" #include "hw/loader.h" +#include "hw/riscv/riscv_hart.h" -bool riscv_is_32_bit(MachineState *machine); +bool riscv_is_32bit(RISCVHartArrayState harts); -target_ulong riscv_calc_kernel_start_addr(MachineState *machine, +target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState harts, target_ulong firmware_end_addr); target_ulong riscv_find_and_load_firmware(MachineState *machine, const char *default_machine_firmware, @@ -41,10 +42,13 @@ target_ulong riscv_load_kernel(const char *kernel_filename, hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, uint64_t kernel_entry, hwaddr *start); uint32_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); -void riscv_setup_rom_reset_vec(hwaddr saddr, hwaddr rom_base, - hwaddr rom_size, uint64_t kernel_entry, +void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState harts, + hwaddr saddr, + hwaddr rom_base, hwaddr rom_size, + uint64_t kernel_entry, uint32_t fdt_load_addr, void *fdt); -void riscv_rom_copy_firmware_info(hwaddr rom_base, hwaddr rom_size, +void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base, + hwaddr rom_size, uint32_t reset_vec_size, uint64_t kernel_entry); diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h index 51d4463..d0c666a 100644 --- a/include/hw/riscv/microchip_pfsoc.h +++ b/include/hw/riscv/microchip_pfsoc.h @@ -97,6 +97,8 @@ enum { MICROCHIP_PFSOC_MMUART2, MICROCHIP_PFSOC_MMUART3, MICROCHIP_PFSOC_MMUART4, + MICROCHIP_PFSOC_SPI0, + MICROCHIP_PFSOC_SPI1, MICROCHIP_PFSOC_I2C1, MICROCHIP_PFSOC_GEM0, MICROCHIP_PFSOC_GEM1, @@ -105,6 +107,7 @@ enum { MICROCHIP_PFSOC_GPIO2, MICROCHIP_PFSOC_ENVM_CFG, MICROCHIP_PFSOC_ENVM_DATA, + MICROCHIP_PFSOC_QSPI_XIP, MICROCHIP_PFSOC_IOSCB, MICROCHIP_PFSOC_DRAM_LO, MICROCHIP_PFSOC_DRAM_LO_ALIAS, diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h index 5ff0c0f..a5ea3a5 100644 --- a/include/hw/riscv/opentitan.h +++ b/include/hw/riscv/opentitan.h @@ -55,19 +55,30 @@ enum { IBEX_DEV_UART, IBEX_DEV_GPIO, IBEX_DEV_SPI, - IBEX_DEV_FLASH_CTRL, + IBEX_DEV_I2C, + IBEX_DEV_PATTGEN, IBEX_DEV_RV_TIMER, - IBEX_DEV_AES, - IBEX_DEV_HMAC, - IBEX_DEV_PLIC, + IBEX_DEV_SENSOR_CTRL, + IBEX_DEV_OTP_CTRL, IBEX_DEV_PWRMGR, IBEX_DEV_RSTMGR, IBEX_DEV_CLKMGR, IBEX_DEV_PINMUX, + IBEX_DEV_PADCTRL, + IBEX_DEV_USBDEV, + IBEX_DEV_FLASH_CTRL, + IBEX_DEV_PLIC, + IBEX_DEV_AES, + IBEX_DEV_HMAC, + IBEX_DEV_KMAC, + IBEX_DEV_KEYMGR, + IBEX_DEV_CSRNG, + IBEX_DEV_ENTROPY, + IBEX_DEV_EDNO, + IBEX_DEV_EDN1, IBEX_DEV_ALERT_HANDLER, IBEX_DEV_NMI_GEN, - IBEX_DEV_USBDEV, - IBEX_DEV_PADCTRL, + IBEX_DEV_OTBN, }; enum { diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h index cddeca2..cdd1a13 100644 --- a/include/hw/riscv/spike.h +++ b/include/hw/riscv/spike.h @@ -47,10 +47,4 @@ enum { SPIKE_DRAM }; -#if defined(TARGET_RISCV32) -#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE32 -#elif defined(TARGET_RISCV64) -#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE64 -#endif - #endif diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index b4ed9a3..84b7a38 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -89,10 +89,4 @@ enum { #define FDT_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + 1 + \ FDT_PLIC_ADDR_CELLS + FDT_PLIC_INT_CELLS) -#if defined(TARGET_RISCV32) -#define VIRT_CPU TYPE_RISCV_CPU_BASE32 -#elif defined(TARGET_RISCV64) -#define VIRT_CPU TYPE_RISCV_CPU_BASE64 -#endif - #endif |