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-rw-r--r--include/hw/ppc/pnv.h146
-rw-r--r--include/hw/ppc/pnv_chip.h147
-rw-r--r--include/hw/ppc/pnv_core.h3
-rw-r--r--include/hw/ppc/pnv_homer.h2
-rw-r--r--include/hw/ppc/pnv_lpc.h11
-rw-r--r--include/hw/ppc/pnv_occ.h3
-rw-r--r--include/hw/ppc/pnv_pnor.h2
-rw-r--r--include/hw/ppc/pnv_sbe.h3
-rw-r--r--include/hw/ppc/pnv_xive.h7
-rw-r--r--include/hw/ppc/pnv_xscom.h3
-rw-r--r--include/hw/ppc/xive2.h2
-rw-r--r--include/hw/ppc/xive2_regs.h2
12 files changed, 171 insertions, 160 deletions
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 9ef7e2d..96fb850 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -20,158 +20,18 @@
#ifndef PPC_PNV_H
#define PPC_PNV_H
+#include "cpu.h"
#include "hw/boards.h"
#include "hw/sysbus.h"
#include "hw/ipmi/ipmi.h"
-#include "hw/ppc/pnv_lpc.h"
#include "hw/ppc/pnv_pnor.h"
-#include "hw/ppc/pnv_psi.h"
-#include "hw/ppc/pnv_occ.h"
-#include "hw/ppc/pnv_sbe.h"
-#include "hw/ppc/pnv_homer.h"
-#include "hw/ppc/pnv_xive.h"
-#include "hw/ppc/pnv_core.h"
-#include "hw/pci-host/pnv_phb3.h"
-#include "hw/pci-host/pnv_phb4.h"
-#include "hw/pci-host/pnv_phb.h"
-#include "qom/object.h"
#define TYPE_PNV_CHIP "pnv-chip"
-OBJECT_DECLARE_TYPE(PnvChip, PnvChipClass,
- PNV_CHIP)
-struct PnvChip {
- /*< private >*/
- SysBusDevice parent_obj;
-
- /*< public >*/
- uint32_t chip_id;
- uint64_t ram_start;
- uint64_t ram_size;
-
- uint32_t nr_cores;
- uint32_t nr_threads;
- uint64_t cores_mask;
- PnvCore **cores;
-
- uint32_t num_pecs;
-
- MemoryRegion xscom_mmio;
- MemoryRegion xscom;
- AddressSpace xscom_as;
-
- MemoryRegion *fw_mr;
- gchar *dt_isa_nodename;
-};
-
-#define TYPE_PNV8_CHIP "pnv8-chip"
+typedef struct PnvChip PnvChip;
typedef struct Pnv8Chip Pnv8Chip;
-DECLARE_INSTANCE_CHECKER(Pnv8Chip, PNV8_CHIP,
- TYPE_PNV8_CHIP)
-
-struct Pnv8Chip {
- /*< private >*/
- PnvChip parent_obj;
-
- /*< public >*/
- MemoryRegion icp_mmio;
-
- PnvLpcController lpc;
- Pnv8Psi psi;
- PnvOCC occ;
- PnvHomer homer;
-
-#define PNV8_CHIP_PHB3_MAX 4
- /*
- * The array is used to allow quick access to the phbs by
- * pnv_ics_get_child() and pnv_ics_resend_child().
- */
- PnvPHB *phbs[PNV8_CHIP_PHB3_MAX];
- uint32_t num_phbs;
-
- XICSFabric *xics;
-};
-
-#define TYPE_PNV9_CHIP "pnv9-chip"
typedef struct Pnv9Chip Pnv9Chip;
-DECLARE_INSTANCE_CHECKER(Pnv9Chip, PNV9_CHIP,
- TYPE_PNV9_CHIP)
-
-struct Pnv9Chip {
- /*< private >*/
- PnvChip parent_obj;
-
- /*< public >*/
- PnvXive xive;
- Pnv9Psi psi;
- PnvLpcController lpc;
- PnvOCC occ;
- PnvSBE sbe;
- PnvHomer homer;
-
- uint32_t nr_quads;
- PnvQuad *quads;
-
-#define PNV9_CHIP_MAX_PEC 3
- PnvPhb4PecState pecs[PNV9_CHIP_MAX_PEC];
-};
-
-/*
- * A SMT8 fused core is a pair of SMT4 cores.
- */
-#define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
-#define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f)
-
-#define TYPE_PNV10_CHIP "pnv10-chip"
typedef struct Pnv10Chip Pnv10Chip;
-DECLARE_INSTANCE_CHECKER(Pnv10Chip, PNV10_CHIP,
- TYPE_PNV10_CHIP)
-
-struct Pnv10Chip {
- /*< private >*/
- PnvChip parent_obj;
-
- /*< public >*/
- PnvXive2 xive;
- Pnv9Psi psi;
- PnvLpcController lpc;
- PnvOCC occ;
- PnvSBE sbe;
- PnvHomer homer;
-
- uint32_t nr_quads;
- PnvQuad *quads;
-
-#define PNV10_CHIP_MAX_PEC 2
- PnvPhb4PecState pecs[PNV10_CHIP_MAX_PEC];
-};
-
-#define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
-#define PNV10_PIR2CHIP(pir) (((pir) >> 8) & 0x7f)
-
-struct PnvChipClass {
- /*< private >*/
- SysBusDeviceClass parent_class;
-
- /*< public >*/
- uint64_t chip_cfam_id;
- uint64_t cores_mask;
- uint32_t num_pecs;
- uint32_t num_phbs;
-
- DeviceRealize parent_realize;
-
- uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
- void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp);
- void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu);
- void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu);
- void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, Monitor *mon);
- ISABus *(*isa_create)(PnvChip *chip, Error **errp);
- void (*dt_populate)(PnvChip *chip, void *fdt);
- void (*pic_print_info)(PnvChip *chip, Monitor *mon);
- uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id);
- uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr);
-};
#define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP
#define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX
@@ -198,6 +58,8 @@ DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10,
PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir);
+typedef struct PnvPHB PnvPHB;
+
#define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv")
typedef struct PnvMachineClass PnvMachineClass;
typedef struct PnvMachineState PnvMachineState;
diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h
new file mode 100644
index 0000000..53e1d92
--- /dev/null
+++ b/include/hw/ppc/pnv_chip.h
@@ -0,0 +1,147 @@
+#ifndef PPC_PNV_CHIP_H
+#define PPC_PNV_CHIP_H
+
+#include "hw/pci-host/pnv_phb4.h"
+#include "hw/ppc/pnv_core.h"
+#include "hw/ppc/pnv_homer.h"
+#include "hw/ppc/pnv_lpc.h"
+#include "hw/ppc/pnv_occ.h"
+#include "hw/ppc/pnv_psi.h"
+#include "hw/ppc/pnv_sbe.h"
+#include "hw/ppc/pnv_xive.h"
+#include "hw/sysbus.h"
+
+OBJECT_DECLARE_TYPE(PnvChip, PnvChipClass,
+ PNV_CHIP)
+
+struct PnvChip {
+ /*< private >*/
+ SysBusDevice parent_obj;
+
+ /*< public >*/
+ uint32_t chip_id;
+ uint64_t ram_start;
+ uint64_t ram_size;
+
+ uint32_t nr_cores;
+ uint32_t nr_threads;
+ uint64_t cores_mask;
+ PnvCore **cores;
+
+ uint32_t num_pecs;
+
+ MemoryRegion xscom_mmio;
+ MemoryRegion xscom;
+ AddressSpace xscom_as;
+
+ MemoryRegion *fw_mr;
+ gchar *dt_isa_nodename;
+};
+
+#define TYPE_PNV8_CHIP "pnv8-chip"
+DECLARE_INSTANCE_CHECKER(Pnv8Chip, PNV8_CHIP,
+ TYPE_PNV8_CHIP)
+
+struct Pnv8Chip {
+ /*< private >*/
+ PnvChip parent_obj;
+
+ /*< public >*/
+ MemoryRegion icp_mmio;
+
+ PnvLpcController lpc;
+ Pnv8Psi psi;
+ PnvOCC occ;
+ PnvHomer homer;
+
+#define PNV8_CHIP_PHB3_MAX 4
+ /*
+ * The array is used to allow quick access to the phbs by
+ * pnv_ics_get_child() and pnv_ics_resend_child().
+ */
+ PnvPHB *phbs[PNV8_CHIP_PHB3_MAX];
+ uint32_t num_phbs;
+
+ XICSFabric *xics;
+};
+
+#define TYPE_PNV9_CHIP "pnv9-chip"
+DECLARE_INSTANCE_CHECKER(Pnv9Chip, PNV9_CHIP,
+ TYPE_PNV9_CHIP)
+
+struct Pnv9Chip {
+ /*< private >*/
+ PnvChip parent_obj;
+
+ /*< public >*/
+ PnvXive xive;
+ Pnv9Psi psi;
+ PnvLpcController lpc;
+ PnvOCC occ;
+ PnvSBE sbe;
+ PnvHomer homer;
+
+ uint32_t nr_quads;
+ PnvQuad *quads;
+
+#define PNV9_CHIP_MAX_PEC 3
+ PnvPhb4PecState pecs[PNV9_CHIP_MAX_PEC];
+};
+
+/*
+ * A SMT8 fused core is a pair of SMT4 cores.
+ */
+#define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
+#define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f)
+
+#define TYPE_PNV10_CHIP "pnv10-chip"
+DECLARE_INSTANCE_CHECKER(Pnv10Chip, PNV10_CHIP,
+ TYPE_PNV10_CHIP)
+
+struct Pnv10Chip {
+ /*< private >*/
+ PnvChip parent_obj;
+
+ /*< public >*/
+ PnvXive2 xive;
+ Pnv9Psi psi;
+ PnvLpcController lpc;
+ PnvOCC occ;
+ PnvSBE sbe;
+ PnvHomer homer;
+
+ uint32_t nr_quads;
+ PnvQuad *quads;
+
+#define PNV10_CHIP_MAX_PEC 2
+ PnvPhb4PecState pecs[PNV10_CHIP_MAX_PEC];
+};
+
+#define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
+#define PNV10_PIR2CHIP(pir) (((pir) >> 8) & 0x7f)
+
+struct PnvChipClass {
+ /*< private >*/
+ SysBusDeviceClass parent_class;
+
+ /*< public >*/
+ uint64_t chip_cfam_id;
+ uint64_t cores_mask;
+ uint32_t num_pecs;
+ uint32_t num_phbs;
+
+ DeviceRealize parent_realize;
+
+ uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
+ void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp);
+ void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu);
+ void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu);
+ void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, Monitor *mon);
+ ISABus *(*isa_create)(PnvChip *chip, Error **errp);
+ void (*dt_populate)(PnvChip *chip, void *fdt);
+ void (*pic_print_info)(PnvChip *chip, Monitor *mon);
+ uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id);
+ uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr);
+};
+
+#endif
diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h
index c22eab2..3d75706 100644
--- a/include/hw/ppc/pnv_core.h
+++ b/include/hw/ppc/pnv_core.h
@@ -22,14 +22,13 @@
#include "hw/cpu/core.h"
#include "target/ppc/cpu.h"
+#include "hw/ppc/pnv.h"
#include "qom/object.h"
#define TYPE_PNV_CORE "powernv-cpu-core"
OBJECT_DECLARE_TYPE(PnvCore, PnvCoreClass,
PNV_CORE)
-typedef struct PnvChip PnvChip;
-
struct PnvCore {
/*< private >*/
CPUCore parent_obj;
diff --git a/include/hw/ppc/pnv_homer.h b/include/hw/ppc/pnv_homer.h
index 07e8b19..b1c5d49 100644
--- a/include/hw/ppc/pnv_homer.h
+++ b/include/hw/ppc/pnv_homer.h
@@ -39,7 +39,7 @@ DECLARE_INSTANCE_CHECKER(PnvHomer, PNV10_HOMER,
struct PnvHomer {
DeviceState parent;
- struct PnvChip *chip;
+ PnvChip *chip;
MemoryRegion pba_regs;
MemoryRegion regs;
};
diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h
index 8a8d1a3..5d22c45 100644
--- a/include/hw/ppc/pnv_lpc.h
+++ b/include/hw/ppc/pnv_lpc.h
@@ -20,7 +20,9 @@
#ifndef PPC_PNV_LPC_H
#define PPC_PNV_LPC_H
-#include "qom/object.h"
+#include "exec/memory.h"
+#include "hw/ppc/pnv.h"
+#include "hw/qdev-core.h"
#define TYPE_PNV_LPC "pnv-lpc"
typedef struct PnvLpcClass PnvLpcClass;
@@ -92,13 +94,8 @@ struct PnvLpcClass {
DeviceRealize parent_realize;
};
-/*
- * Old compilers error on typdef forward declarations. Keep them happy.
- */
-struct PnvChip;
-
ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **errp);
-int pnv_dt_lpc(struct PnvChip *chip, void *fdt, int root_offset,
+int pnv_dt_lpc(PnvChip *chip, void *fdt, int root_offset,
uint64_t lpcm_addr, uint64_t lpcm_size);
#endif /* PPC_PNV_LPC_H */
diff --git a/include/hw/ppc/pnv_occ.h b/include/hw/ppc/pnv_occ.h
index 90a81da..df32124 100644
--- a/include/hw/ppc/pnv_occ.h
+++ b/include/hw/ppc/pnv_occ.h
@@ -20,7 +20,8 @@
#ifndef PPC_PNV_OCC_H
#define PPC_PNV_OCC_H
-#include "qom/object.h"
+#include "exec/memory.h"
+#include "hw/qdev-core.h"
#define TYPE_PNV_OCC "pnv-occ"
OBJECT_DECLARE_TYPE(PnvOCC, PnvOCCClass,
diff --git a/include/hw/ppc/pnv_pnor.h b/include/hw/ppc/pnv_pnor.h
index bab2f79..2e37ac8 100644
--- a/include/hw/ppc/pnv_pnor.h
+++ b/include/hw/ppc/pnv_pnor.h
@@ -10,7 +10,7 @@
#ifndef PPC_PNV_PNOR_H
#define PPC_PNV_PNOR_H
-#include "qom/object.h"
+#include "hw/sysbus.h"
/*
* PNOR offset on the LPC FW address space
diff --git a/include/hw/ppc/pnv_sbe.h b/include/hw/ppc/pnv_sbe.h
index f54a3ae..b6b378a 100644
--- a/include/hw/ppc/pnv_sbe.h
+++ b/include/hw/ppc/pnv_sbe.h
@@ -20,7 +20,8 @@
#ifndef PPC_PNV_SBE_H
#define PPC_PNV_SBE_H
-#include "qom/object.h"
+#include "exec/memory.h"
+#include "hw/qdev-core.h"
#define TYPE_PNV_SBE "pnv-sbe"
OBJECT_DECLARE_TYPE(PnvSBE, PnvSBEClass, PNV_SBE)
diff --git a/include/hw/ppc/pnv_xive.h b/include/hw/ppc/pnv_xive.h
index b5d9150..9c48430 100644
--- a/include/hw/ppc/pnv_xive.h
+++ b/include/hw/ppc/pnv_xive.h
@@ -10,12 +10,11 @@
#ifndef PPC_PNV_XIVE_H
#define PPC_PNV_XIVE_H
+#include "hw/ppc/pnv.h"
#include "hw/ppc/xive.h"
#include "qom/object.h"
#include "hw/ppc/xive2.h"
-struct PnvChip;
-
#define TYPE_PNV_XIVE "pnv-xive"
OBJECT_DECLARE_TYPE(PnvXive, PnvXiveClass,
PNV_XIVE)
@@ -31,7 +30,7 @@ struct PnvXive {
XiveRouter parent_obj;
/* Owning chip */
- struct PnvChip *chip;
+ PnvChip *chip;
/* XSCOM addresses giving access to the controller registers */
MemoryRegion xscom_regs;
@@ -106,7 +105,7 @@ typedef struct PnvXive2 {
Xive2Router parent_obj;
/* Owning chip */
- struct PnvChip *chip;
+ PnvChip *chip;
/* XSCOM addresses giving access to the controller registers */
MemoryRegion xscom_regs;
diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
index c6e9ef8..cbe848d 100644
--- a/include/hw/ppc/pnv_xscom.h
+++ b/include/hw/ppc/pnv_xscom.h
@@ -20,7 +20,8 @@
#ifndef PPC_PNV_XSCOM_H
#define PPC_PNV_XSCOM_H
-#include "qom/object.h"
+#include "exec/memory.h"
+#include "hw/ppc/pnv.h"
typedef struct PnvXScomInterface PnvXScomInterface;
diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h
index e9e3ea1..ab68f8d 100644
--- a/include/hw/ppc/xive2.h
+++ b/include/hw/ppc/xive2.h
@@ -11,7 +11,9 @@
#ifndef PPC_XIVE2_H
#define PPC_XIVE2_H
+#include "hw/ppc/xive.h"
#include "hw/ppc/xive2_regs.h"
+#include "hw/sysbus.h"
/*
* XIVE2 Router (POWER10)
diff --git a/include/hw/ppc/xive2_regs.h b/include/hw/ppc/xive2_regs.h
index 14605bd..b7adbdb 100644
--- a/include/hw/ppc/xive2_regs.h
+++ b/include/hw/ppc/xive2_regs.h
@@ -10,6 +10,8 @@
#ifndef PPC_XIVE2_REGS_H
#define PPC_XIVE2_REGS_H
+#include "cpu.h"
+
/*
* Thread Interrupt Management Area (TIMA)
*
generated by cgit v1.1 at 2025-01-15 05:32:24 +0000