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-rw-r--r--hw/arm/armv7m.c2
-rw-r--r--hw/display/vga.c2
-rw-r--r--hw/microblaze/boot.c2
-rw-r--r--hw/mips/gt64xxx_pci.c6
-rw-r--r--hw/mips/jazz.c2
-rw-r--r--hw/mips/malta.c24
-rw-r--r--hw/mips/mipssim.c2
-rw-r--r--hw/nios2/boot.c2
-rw-r--r--hw/xtensa/sim.c2
-rw-r--r--hw/xtensa/xtfpga.c4
10 files changed, 24 insertions, 24 deletions
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
index 41cfca0..32349ec 100644
--- a/hw/arm/armv7m.c
+++ b/hw/arm/armv7m.c
@@ -577,7 +577,7 @@ void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size)
int asidx;
CPUState *cs = CPU(cpu);
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
big_endian = 1;
#else
big_endian = 0;
diff --git a/hw/display/vga.c b/hw/display/vga.c
index 737cfbd..5dca2d1 100644
--- a/hw/display/vga.c
+++ b/hw/display/vga.c
@@ -2242,7 +2242,7 @@ bool vga_common_init(VGACommonState *s, Object *obj, Error **errp)
* into a device attribute set by the machine/platform to remove
* all target endian dependencies from this file.
*/
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
s->default_endian_fb = true;
#else
s->default_endian_fb = false;
diff --git a/hw/microblaze/boot.c b/hw/microblaze/boot.c
index 8821d00..03c030a 100644
--- a/hw/microblaze/boot.c
+++ b/hw/microblaze/boot.c
@@ -138,7 +138,7 @@ void microblaze_load_kernel(MicroBlazeCPU *cpu, hwaddr ddr_base,
uint32_t base32;
int big_endian = 0;
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
big_endian = 1;
#endif
diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c
index e0ff1b5..19d0d98 100644
--- a/hw/mips/gt64xxx_pci.c
+++ b/hw/mips/gt64xxx_pci.c
@@ -986,7 +986,7 @@ static void gt64120_reset(DeviceState *dev)
/* FIXME: Malta specific hw assumptions ahead */
/* CPU Configuration */
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
s->regs[GT_CPU] = 0x00000000;
#else
s->regs[GT_CPU] = 0x00001000;
@@ -1097,7 +1097,7 @@ static void gt64120_reset(DeviceState *dev)
s->regs[GT_TC_CONTROL] = 0x00000000;
/* PCI Internal */
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
s->regs[GT_PCI0_CMD] = 0x00000000;
#else
s->regs[GT_PCI0_CMD] = 0x00010001;
@@ -1118,7 +1118,7 @@ static void gt64120_reset(DeviceState *dev)
s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000;
s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000;
s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000;
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
s->regs[GT_PCI1_CMD] = 0x00000000;
#else
s->regs[GT_PCI1_CMD] = 0x00010001;
diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c
index 44f0d48..4d6b44d 100644
--- a/hw/mips/jazz.c
+++ b/hw/mips/jazz.c
@@ -158,7 +158,7 @@ static void mips_jazz_init(MachineState *machine,
[JAZZ_PICA61] = {33333333, 4},
};
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
big_endian = 1;
#else
big_endian = 0;
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 6288511..c4474b9 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -367,7 +367,7 @@ static uint64_t malta_fpga_read(void *opaque, hwaddr addr,
/* STATUS Register */
case 0x00208:
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
val = 0x00000012;
#else
val = 0x00000010;
@@ -695,7 +695,7 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
stw_p(p++, 0xe040); stw_p(p++, 0x0681);
/* lui t1, %hi(0xb4000000) */
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
stw_p(p++, 0xe020); stw_p(p++, 0x0be1);
/* lui t0, %hi(0xdf000000) */
@@ -894,7 +894,7 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr,
/* Load BAR registers as done by YAMON */
stl_p(p++, 0x3c09b400); /* lui t1, 0xb400 */
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
stl_p(p++, 0x3c08df00); /* lui t0, 0xdf00 */
#else
stl_p(p++, 0x340800df); /* ori t0, r0, 0x00df */
@@ -903,39 +903,39 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr,
stl_p(p++, 0x3c09bbe0); /* lui t1, 0xbbe0 */
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
stl_p(p++, 0x3c08c000); /* lui t0, 0xc000 */
#else
stl_p(p++, 0x340800c0); /* ori t0, r0, 0x00c0 */
#endif
stl_p(p++, 0xad280048); /* sw t0, 0x0048(t1) */
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
stl_p(p++, 0x3c084000); /* lui t0, 0x4000 */
#else
stl_p(p++, 0x34080040); /* ori t0, r0, 0x0040 */
#endif
stl_p(p++, 0xad280050); /* sw t0, 0x0050(t1) */
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
stl_p(p++, 0x3c088000); /* lui t0, 0x8000 */
#else
stl_p(p++, 0x34080080); /* ori t0, r0, 0x0080 */
#endif
stl_p(p++, 0xad280058); /* sw t0, 0x0058(t1) */
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
stl_p(p++, 0x3c083f00); /* lui t0, 0x3f00 */
#else
stl_p(p++, 0x3408003f); /* ori t0, r0, 0x003f */
#endif
stl_p(p++, 0xad280060); /* sw t0, 0x0060(t1) */
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
stl_p(p++, 0x3c08c100); /* lui t0, 0xc100 */
#else
stl_p(p++, 0x340800c1); /* ori t0, r0, 0x00c1 */
#endif
stl_p(p++, 0xad280080); /* sw t0, 0x0080(t1) */
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
stl_p(p++, 0x3c085e00); /* lui t0, 0x5e00 */
#else
stl_p(p++, 0x3408005e); /* ori t0, r0, 0x005e */
@@ -1030,7 +1030,7 @@ static uint64_t load_kernel(void)
int prom_index = 0;
uint64_t (*xlate_to_kseg0) (void *opaque, uint64_t addr);
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
big_endian = 1;
#else
big_endian = 0;
@@ -1272,7 +1272,7 @@ void mips_malta_init(MachineState *machine)
ram_low_postio);
}
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
be = 1;
#else
be = 0;
@@ -1353,7 +1353,7 @@ void mips_malta_init(MachineState *machine)
* In little endian mode the 32bit words in the bios are swapped,
* a neat trick which allows bi-endian firmware.
*/
-#ifndef TARGET_WORDS_BIGENDIAN
+#if !TARGET_BIG_ENDIAN
{
uint32_t *end, *addr;
const size_t swapsize = MIN(bios_size, 0x3e0000);
diff --git a/hw/mips/mipssim.c b/hw/mips/mipssim.c
index 27a46bd..30bc1c4 100644
--- a/hw/mips/mipssim.c
+++ b/hw/mips/mipssim.c
@@ -65,7 +65,7 @@ static uint64_t load_kernel(void)
ram_addr_t initrd_offset;
int big_endian;
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
big_endian = 1;
#else
big_endian = 0;
diff --git a/hw/nios2/boot.c b/hw/nios2/boot.c
index 5b3e4ef..e889595 100644
--- a/hw/nios2/boot.c
+++ b/hw/nios2/boot.c
@@ -140,7 +140,7 @@ void nios2_load_kernel(Nios2CPU *cpu, hwaddr ddr_base,
uint64_t entry, high;
int big_endian = 0;
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
big_endian = 1;
#endif
diff --git a/hw/xtensa/sim.c b/hw/xtensa/sim.c
index 2028fe7..946c71c 100644
--- a/hw/xtensa/sim.c
+++ b/hw/xtensa/sim.c
@@ -96,7 +96,7 @@ XtensaCPU *xtensa_sim_common_init(MachineState *machine)
void xtensa_sim_load_kernel(XtensaCPU *cpu, MachineState *machine)
{
const char *kernel_filename = machine->kernel_filename;
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
int big_endian = true;
#else
int big_endian = false;
diff --git a/hw/xtensa/xtfpga.c b/hw/xtensa/xtfpga.c
index c1e004e..2a5556a 100644
--- a/hw/xtensa/xtfpga.c
+++ b/hw/xtensa/xtfpga.c
@@ -219,7 +219,7 @@ static const MemoryRegionOps xtfpga_io_ops = {
static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine)
{
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
int be = 1;
#else
int be = 0;
@@ -430,7 +430,7 @@ static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine)
}
if (entry_point != env->pc) {
uint8_t boot[] = {
-#ifdef TARGET_WORDS_BIGENDIAN
+#if TARGET_BIG_ENDIAN
0x60, 0x00, 0x08, /* j 1f */
0x00, /* .literal_position */
0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */
generated by cgit v1.1 at 2024-09-28 17:52:58 +0000