aboutsummaryrefslogtreecommitdiff
path: root/hw
diff options
context:
space:
mode:
Diffstat (limited to 'hw')
-rw-r--r--hw/mips/cps.c6
-rw-r--r--hw/mips/mips_fulong2e.c96
-rw-r--r--hw/mips/mips_int.c3
-rw-r--r--hw/mips/mips_malta.c216
-rw-r--r--hw/mips/mips_mipssim.c19
5 files changed, 204 insertions, 136 deletions
diff --git a/hw/mips/cps.c b/hw/mips/cps.c
index cd8b07d..1660f86 100644
--- a/hw/mips/cps.c
+++ b/hw/mips/cps.c
@@ -38,8 +38,10 @@ static void mips_cps_init(Object *obj)
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
MIPSCPSState *s = MIPS_CPS(obj);
- /* Cover entire address space as there do not seem to be any
- * constraints for the base address of CPC and GIC. */
+ /*
+ * Cover entire address space as there do not seem to be any
+ * constraints for the base address of CPC and GIC.
+ */
memory_region_init(&s->container, obj, "mips-cps-container", UINT64_MAX);
sysbus_init_mmio(sbd, &s->container);
}
diff --git a/hw/mips/mips_fulong2e.c b/hw/mips/mips_fulong2e.c
index 6e4fba2..cf537dd 100644
--- a/hw/mips/mips_fulong2e.c
+++ b/hw/mips/mips_fulong2e.c
@@ -48,13 +48,13 @@
#define DEBUG_FULONG2E_INIT
-#define ENVP_ADDR 0x80002000l
-#define ENVP_NB_ENTRIES 16
-#define ENVP_ENTRY_SIZE 256
+#define ENVP_ADDR 0x80002000l
+#define ENVP_NB_ENTRIES 16
+#define ENVP_ENTRY_SIZE 256
/* fulong 2e has a 512k flash: Winbond W39L040AP70Z */
-#define BIOS_SIZE (512 * KiB)
-#define MAX_IDE_BUS 2
+#define BIOS_SIZE (512 * KiB)
+#define MAX_IDE_BUS 2
/*
* PMON is not part of qemu and released with BSD license, anyone
@@ -83,14 +83,15 @@ static struct _loaderparams {
const char *initrd_filename;
} loaderparams;
-static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t* prom_buf, int index,
+static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t *prom_buf, int index,
const char *string, ...)
{
va_list ap;
int32_t table_addr;
- if (index >= ENVP_NB_ENTRIES)
+ if (index >= ENVP_NB_ENTRIES) {
return;
+ }
if (string == NULL) {
prom_buf[index] = 0;
@@ -105,7 +106,7 @@ static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t* prom_buf, int index,
va_end(ap);
}
-static int64_t load_kernel (CPUMIPSState *env)
+static int64_t load_kernel(CPUMIPSState *env)
{
int64_t kernel_entry, kernel_low, kernel_high, initrd_size;
int index = 0;
@@ -130,16 +131,18 @@ static int64_t load_kernel (CPUMIPSState *env)
initrd_size = 0;
initrd_offset = 0;
if (loaderparams.initrd_filename) {
- initrd_size = get_image_size (loaderparams.initrd_filename);
+ initrd_size = get_image_size(loaderparams.initrd_filename);
if (initrd_size > 0) {
- initrd_offset = (kernel_high + ~INITRD_PAGE_MASK) & INITRD_PAGE_MASK;
+ initrd_offset = (kernel_high + ~INITRD_PAGE_MASK) &
+ INITRD_PAGE_MASK;
if (initrd_offset + initrd_size > ram_size) {
error_report("memory too small for initial ram disk '%s'",
loaderparams.initrd_filename);
exit(1);
}
initrd_size = load_image_targphys(loaderparams.initrd_filename,
- initrd_offset, ram_size - initrd_offset);
+ initrd_offset,
+ ram_size - initrd_offset);
}
if (initrd_size == (target_ulong) -1) {
error_report("could not load initial ram disk '%s'",
@@ -154,9 +157,10 @@ static int64_t load_kernel (CPUMIPSState *env)
prom_set(prom_buf, index++, "%s", loaderparams.kernel_filename);
if (initrd_size > 0) {
- prom_set(prom_buf, index++, "rd_start=0x%" PRIx64 " rd_size=%" PRId64 " %s",
- cpu_mips_phys_to_kseg0(NULL, initrd_offset), initrd_size,
- loaderparams.kernel_cmdline);
+ prom_set(prom_buf, index++,
+ "rd_start=0x%" PRIx64 " rd_size=%" PRId64 " %s",
+ cpu_mips_phys_to_kseg0(NULL, initrd_offset),
+ initrd_size, loaderparams.kernel_cmdline);
} else {
prom_set(prom_buf, index++, "%s", loaderparams.kernel_cmdline);
}
@@ -175,34 +179,48 @@ static int64_t load_kernel (CPUMIPSState *env)
return kernel_entry;
}
-static void write_bootloader (CPUMIPSState *env, uint8_t *base, int64_t kernel_addr)
+static void write_bootloader(CPUMIPSState *env, uint8_t *base,
+ int64_t kernel_addr)
{
uint32_t *p;
/* Small bootloader */
- p = (uint32_t *) base;
+ p = (uint32_t *)base;
- stl_p(p++, 0x0bf00010); /* j 0x1fc00040 */
- stl_p(p++, 0x00000000); /* nop */
+ /* j 0x1fc00040 */
+ stl_p(p++, 0x0bf00010);
+ /* nop */
+ stl_p(p++, 0x00000000);
/* Second part of the bootloader */
- p = (uint32_t *) (base + 0x040);
-
- stl_p(p++, 0x3c040000); /* lui a0, 0 */
- stl_p(p++, 0x34840002); /* ori a0, a0, 2 */
- stl_p(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff)); /* lui a1, high(ENVP_ADDR) */
- stl_p(p++, 0x34a50000 | (ENVP_ADDR & 0xffff)); /* ori a1, a0, low(ENVP_ADDR) */
- stl_p(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff)); /* lui a2, high(ENVP_ADDR + 8) */
- stl_p(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff)); /* ori a2, a2, low(ENVP_ADDR + 8) */
- stl_p(p++, 0x3c070000 | (loaderparams.ram_size >> 16)); /* lui a3, high(env->ram_size) */
- stl_p(p++, 0x34e70000 | (loaderparams.ram_size & 0xffff)); /* ori a3, a3, low(env->ram_size) */
- stl_p(p++, 0x3c1f0000 | ((kernel_addr >> 16) & 0xffff)); /* lui ra, high(kernel_addr) */;
- stl_p(p++, 0x37ff0000 | (kernel_addr & 0xffff)); /* ori ra, ra, low(kernel_addr) */
- stl_p(p++, 0x03e00008); /* jr ra */
- stl_p(p++, 0x00000000); /* nop */
+ p = (uint32_t *)(base + 0x040);
+
+ /* lui a0, 0 */
+ stl_p(p++, 0x3c040000);
+ /* ori a0, a0, 2 */
+ stl_p(p++, 0x34840002);
+ /* lui a1, high(ENVP_ADDR) */
+ stl_p(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff));
+ /* ori a1, a0, low(ENVP_ADDR) */
+ stl_p(p++, 0x34a50000 | (ENVP_ADDR & 0xffff));
+ /* lui a2, high(ENVP_ADDR + 8) */
+ stl_p(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff));
+ /* ori a2, a2, low(ENVP_ADDR + 8) */
+ stl_p(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff));
+ /* lui a3, high(env->ram_size) */
+ stl_p(p++, 0x3c070000 | (loaderparams.ram_size >> 16));
+ /* ori a3, a3, low(env->ram_size) */
+ stl_p(p++, 0x34e70000 | (loaderparams.ram_size & 0xffff));
+ /* lui ra, high(kernel_addr) */
+ stl_p(p++, 0x3c1f0000 | ((kernel_addr >> 16) & 0xffff));
+ /* ori ra, ra, low(kernel_addr) */
+ stl_p(p++, 0x37ff0000 | (kernel_addr & 0xffff));
+ /* jr ra */
+ stl_p(p++, 0x03e00008);
+ /* nop */
+ stl_p(p++, 0x00000000);
}
-
static void main_cpu_reset(void *opaque)
{
MIPSCPU *cpu = opaque;
@@ -252,11 +270,11 @@ static void vt82c686b_southbridge_init(PCIBus *pci_bus, int slot, qemu_irq intc,
}
/* Network support */
-static void network_init (PCIBus *pci_bus)
+static void network_init(PCIBus *pci_bus)
{
int i;
- for(i = 0; i < nb_nics; i++) {
+ for (i = 0; i < nb_nics; i++) {
NICInfo *nd = &nd_table[i];
const char *default_devaddr = NULL;
@@ -308,15 +326,17 @@ static void mips_fulong2e_init(MachineState *machine)
memory_region_add_subregion(address_space_mem, 0, ram);
memory_region_add_subregion(address_space_mem, 0x1fc00000LL, bios);
- /* We do not support flash operation, just loading pmon.bin as raw BIOS.
- * Please use -L to set the BIOS path and -bios to set bios name. */
+ /*
+ * We do not support flash operation, just loading pmon.bin as raw BIOS.
+ * Please use -L to set the BIOS path and -bios to set bios name.
+ */
if (kernel_filename) {
loaderparams.ram_size = ram_size;
loaderparams.kernel_filename = kernel_filename;
loaderparams.kernel_cmdline = kernel_cmdline;
loaderparams.initrd_filename = initrd_filename;
- kernel_entry = load_kernel (env);
+ kernel_entry = load_kernel(env);
write_bootloader(env, memory_region_get_ram_ptr(bios), kernel_entry);
} else {
if (bios_name == NULL) {
diff --git a/hw/mips/mips_int.c b/hw/mips/mips_int.c
index 74cf587..5ebc961 100644
--- a/hw/mips/mips_int.c
+++ b/hw/mips/mips_int.c
@@ -35,8 +35,9 @@ static void cpu_mips_irq_request(void *opaque, int irq, int level)
CPUState *cs = CPU(cpu);
bool locked = false;
- if (irq < 0 || irq > 7)
+ if (irq < 0 || irq > 7) {
return;
+ }
/* Make sure locking works even if BQL is already held by the caller */
if (!qemu_mutex_iothread_locked()) {
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 9fec2b0..4d9c64b 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -60,18 +60,18 @@
#include "hw/semihosting/semihost.h"
#include "hw/mips/cps.h"
-#define ENVP_ADDR 0x80002000l
-#define ENVP_NB_ENTRIES 16
-#define ENVP_ENTRY_SIZE 256
+#define ENVP_ADDR 0x80002000l
+#define ENVP_NB_ENTRIES 16
+#define ENVP_ENTRY_SIZE 256
/* Hardware addresses */
-#define FLASH_ADDRESS 0x1e000000ULL
-#define FPGA_ADDRESS 0x1f000000ULL
-#define RESET_ADDRESS 0x1fc00000ULL
+#define FLASH_ADDRESS 0x1e000000ULL
+#define FPGA_ADDRESS 0x1f000000ULL
+#define RESET_ADDRESS 0x1fc00000ULL
-#define FLASH_SIZE 0x400000
+#define FLASH_SIZE 0x400000
-#define MAX_IDE_BUS 2
+#define MAX_IDE_BUS 2
typedef struct {
MemoryRegion iomem;
@@ -117,10 +117,11 @@ static void malta_fpga_update_display(void *opaque)
MaltaFPGAState *s = opaque;
for (i = 7 ; i >= 0 ; i--) {
- if (s->leds & (1 << i))
+ if (s->leds & (1 << i)) {
leds_text[i] = '#';
- else
+ } else {
leds_text[i] = ' ';
+ }
}
leds_text[8] = '\0';
@@ -140,8 +141,6 @@ static void malta_fpga_update_display(void *opaque)
* Typical device names include Microchip 24C02SC or SGS Thomson ST24C02.
*/
-//~ #define DEBUG
-
#if defined(DEBUG)
# define logout(fmt, ...) fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ## __VA_ARGS__)
#else
@@ -156,7 +155,7 @@ struct _eeprom24c0x_t {
uint8_t scl;
uint8_t sda;
uint8_t data;
- //~ uint16_t size;
+ /* uint16_t size; */
uint8_t contents[256];
};
@@ -164,22 +163,38 @@ typedef struct _eeprom24c0x_t eeprom24c0x_t;
static eeprom24c0x_t spd_eeprom = {
.contents = {
- /* 00000000: */ 0x80,0x08,0xFF,0x0D,0x0A,0xFF,0x40,0x00,
- /* 00000008: */ 0x01,0x75,0x54,0x00,0x82,0x08,0x00,0x01,
- /* 00000010: */ 0x8F,0x04,0x02,0x01,0x01,0x00,0x00,0x00,
- /* 00000018: */ 0x00,0x00,0x00,0x14,0x0F,0x14,0x2D,0xFF,
- /* 00000020: */ 0x15,0x08,0x15,0x08,0x00,0x00,0x00,0x00,
- /* 00000028: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- /* 00000030: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- /* 00000038: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x12,0xD0,
- /* 00000040: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- /* 00000048: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- /* 00000050: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- /* 00000058: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- /* 00000060: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- /* 00000068: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- /* 00000070: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- /* 00000078: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x64,0xF4,
+ /* 00000000: */
+ 0x80, 0x08, 0xFF, 0x0D, 0x0A, 0xFF, 0x40, 0x00,
+ /* 00000008: */
+ 0x01, 0x75, 0x54, 0x00, 0x82, 0x08, 0x00, 0x01,
+ /* 00000010: */
+ 0x8F, 0x04, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00,
+ /* 00000018: */
+ 0x00, 0x00, 0x00, 0x14, 0x0F, 0x14, 0x2D, 0xFF,
+ /* 00000020: */
+ 0x15, 0x08, 0x15, 0x08, 0x00, 0x00, 0x00, 0x00,
+ /* 00000028: */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 00000030: */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 00000038: */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0xD0,
+ /* 00000040: */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 00000048: */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 00000050: */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 00000058: */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 00000060: */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 00000068: */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 00000070: */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 00000078: */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x64, 0xF4,
},
};
@@ -349,7 +364,8 @@ static uint64_t malta_fpga_read(void *opaque, hwaddr addr,
/* SWITCH Register */
case 0x00200:
- val = 0x00000000; /* All switches closed */
+ /* ori a3, a3, low(ram_low_size) */
+ val = 0x00000000;
break;
/* STATUS Register */
@@ -388,10 +404,11 @@ static uint64_t malta_fpga_read(void *opaque, hwaddr addr,
/* GPINP Register */
case 0x00a08:
/* IN = OUT until a real I2C control is implemented */
- if (s->i2csel)
+ if (s->i2csel) {
val = s->i2cout;
- else
+ } else {
val = 0x00;
+ }
break;
/* I2CINP Register */
@@ -416,8 +433,8 @@ static uint64_t malta_fpga_read(void *opaque, hwaddr addr,
default:
#if 0
- printf ("malta_fpga_read: Bad register offset 0x" TARGET_FMT_lx "\n",
- addr);
+ printf("malta_fpga_read: Bad register offset 0x" TARGET_FMT_lx "\n",
+ addr);
#endif
break;
}
@@ -469,8 +486,9 @@ static void malta_fpga_write(void *opaque, hwaddr addr,
/* SOFTRES Register */
case 0x00500:
- if (val == 0x42)
+ if (val == 0x42) {
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+ }
break;
/* BRKRES Register */
@@ -503,8 +521,8 @@ static void malta_fpga_write(void *opaque, hwaddr addr,
default:
#if 0
- printf ("malta_fpga_write: Bad register offset 0x" TARGET_FMT_lx "\n",
- addr);
+ printf("malta_fpga_write: Bad register offset 0x" TARGET_FMT_lx "\n",
+ addr);
#endif
break;
}
@@ -563,7 +581,7 @@ static MaltaFPGAState *malta_fpga_init(MemoryRegion *address_space,
memory_region_init_alias(&s->iomem_lo, NULL, "malta-fpga",
&s->iomem, 0, 0x900);
memory_region_init_alias(&s->iomem_hi, NULL, "malta-fpga",
- &s->iomem, 0xa00, 0x10000-0xa00);
+ &s->iomem, 0xa00, 0x10000 - 0xa00);
memory_region_add_subregion(address_space, base, &s->iomem_lo);
memory_region_add_subregion(address_space, base + 0xa00, &s->iomem_hi);
@@ -587,7 +605,7 @@ static void network_init(PCIBus *pci_bus)
{
int i;
- for(i = 0; i < nb_nics; i++) {
+ for (i = 0; i < nb_nics; i++) {
NICInfo *nd = &nd_table[i];
const char *default_devaddr = NULL;
@@ -801,27 +819,28 @@ static void write_bootloader_nanomips(uint8_t *base, int64_t run_addr,
/* jalrc t8 */
}
-/* ROM and pseudo bootloader
-
- The following code implements a very very simple bootloader. It first
- loads the registers a0 to a3 to the values expected by the OS, and
- then jump at the kernel address.
-
- The bootloader should pass the locations of the kernel arguments and
- environment variables tables. Those tables contain the 32-bit address
- of NULL terminated strings. The environment variables table should be
- terminated by a NULL address.
-
- For a simpler implementation, the number of kernel arguments is fixed
- to two (the name of the kernel and the command line), and the two
- tables are actually the same one.
-
- The registers a0 to a3 should contain the following values:
- a0 - number of kernel arguments
- a1 - 32-bit address of the kernel arguments table
- a2 - 32-bit address of the environment variables table
- a3 - RAM size in bytes
-*/
+/*
+ * ROM and pseudo bootloader
+ *
+ * The following code implements a very very simple bootloader. It first
+ * loads the registers a0 to a3 to the values expected by the OS, and
+ * then jump at the kernel address.
+ *
+ * The bootloader should pass the locations of the kernel arguments and
+ * environment variables tables. Those tables contain the 32-bit address
+ * of NULL terminated strings. The environment variables table should be
+ * terminated by a NULL address.
+ *
+ * For a simpler implementation, the number of kernel arguments is fixed
+ * to two (the name of the kernel and the command line), and the two
+ * tables are actually the same one.
+ *
+ * The registers a0 to a3 should contain the following values:
+ * a0 - number of kernel arguments
+ * a1 - 32-bit address of the kernel arguments table
+ * a2 - 32-bit address of the environment variables table
+ * a3 - RAM size in bytes
+ */
static void write_bootloader(uint8_t *base, int64_t run_addr,
int64_t kernel_entry)
{
@@ -859,14 +878,23 @@ static void write_bootloader(uint8_t *base, int64_t run_addr,
} else {
stl_p(p++, 0x24040002); /* addiu a0, zero, 2 */
}
- stl_p(p++, 0x3c1d0000 | (((ENVP_ADDR - 64) >> 16) & 0xffff)); /* lui sp, high(ENVP_ADDR) */
- stl_p(p++, 0x37bd0000 | ((ENVP_ADDR - 64) & 0xffff)); /* ori sp, sp, low(ENVP_ADDR) */
- stl_p(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff)); /* lui a1, high(ENVP_ADDR) */
- stl_p(p++, 0x34a50000 | (ENVP_ADDR & 0xffff)); /* ori a1, a1, low(ENVP_ADDR) */
- stl_p(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff)); /* lui a2, high(ENVP_ADDR + 8) */
- stl_p(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff)); /* ori a2, a2, low(ENVP_ADDR + 8) */
- stl_p(p++, 0x3c070000 | (loaderparams.ram_low_size >> 16)); /* lui a3, high(ram_low_size) */
- stl_p(p++, 0x34e70000 | (loaderparams.ram_low_size & 0xffff)); /* ori a3, a3, low(ram_low_size) */
+
+ /* lui sp, high(ENVP_ADDR) */
+ stl_p(p++, 0x3c1d0000 | (((ENVP_ADDR - 64) >> 16) & 0xffff));
+ /* ori sp, sp, low(ENVP_ADDR) */
+ stl_p(p++, 0x37bd0000 | ((ENVP_ADDR - 64) & 0xffff));
+ /* lui a1, high(ENVP_ADDR) */
+ stl_p(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff));
+ /* ori a1, a1, low(ENVP_ADDR) */
+ stl_p(p++, 0x34a50000 | (ENVP_ADDR & 0xffff));
+ /* lui a2, high(ENVP_ADDR + 8) */
+ stl_p(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff));
+ /* ori a2, a2, low(ENVP_ADDR + 8) */
+ stl_p(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff));
+ /* lui a3, high(ram_low_size) */
+ stl_p(p++, 0x3c070000 | (loaderparams.ram_low_size >> 16));
+ /* ori a3, a3, low(ram_low_size) */
+ stl_p(p++, 0x34e70000 | (loaderparams.ram_low_size & 0xffff));
/* Load BAR registers as done by YAMON */
stl_p(p++, 0x3c09b400); /* lui t1, 0xb400 */
@@ -970,14 +998,15 @@ static void write_bootloader(uint8_t *base, int64_t run_addr,
}
-static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t* prom_buf, int index,
+static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t *prom_buf, int index,
const char *string, ...)
{
va_list ap;
int32_t table_addr;
- if (index >= ENVP_NB_ENTRIES)
+ if (index >= ENVP_NB_ENTRIES) {
return;
+ }
if (string == NULL) {
prom_buf[index] = 0;
@@ -993,7 +1022,7 @@ static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t* prom_buf, int index,
}
/* Kernel */
-static int64_t load_kernel (void)
+static int64_t load_kernel(void)
{
int64_t kernel_entry, kernel_high, initrd_size;
long kernel_size;
@@ -1041,11 +1070,13 @@ static int64_t load_kernel (void)
initrd_size = 0;
initrd_offset = 0;
if (loaderparams.initrd_filename) {
- initrd_size = get_image_size (loaderparams.initrd_filename);
+ initrd_size = get_image_size(loaderparams.initrd_filename);
if (initrd_size > 0) {
- /* The kernel allocates the bootmap memory in the low memory after
- the initrd. It takes at most 128kiB for 2GB RAM and 4kiB
- pages. */
+ /*
+ * The kernel allocates the bootmap memory in the low memory after
+ * the initrd. It takes at most 128kiB for 2GB RAM and 4kiB
+ * pages.
+ */
initrd_offset = (loaderparams.ram_low_size - initrd_size
- (128 * KiB)
- ~INITRD_PAGE_MASK) & INITRD_PAGE_MASK;
@@ -1071,9 +1102,10 @@ static int64_t load_kernel (void)
prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_filename);
if (initrd_size > 0) {
- prom_set(prom_buf, prom_index++, "rd_start=0x%" PRIx64 " rd_size=%" PRId64 " %s",
- xlate_to_kseg0(NULL, initrd_offset), initrd_size,
- loaderparams.kernel_cmdline);
+ prom_set(prom_buf, prom_index++,
+ "rd_start=0x%" PRIx64 " rd_size=%" PRId64 " %s",
+ xlate_to_kseg0(NULL, initrd_offset),
+ initrd_size, loaderparams.kernel_cmdline);
} else {
prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_cmdline);
}
@@ -1113,9 +1145,11 @@ static void main_cpu_reset(void *opaque)
cpu_reset(CPU(cpu));
- /* The bootloader does not need to be rewritten as it is located in a
- read only location. The kernel location and the arguments table
- location does not change. */
+ /*
+ * The bootloader does not need to be rewritten as it is located in a
+ * read only location. The kernel location and the arguments table
+ * location does not change.
+ */
if (loaderparams.kernel_filename) {
env->CP0_Status &= ~(1 << CP0St_ERL);
}
@@ -1213,9 +1247,11 @@ void mips_malta_init(MachineState *machine)
DeviceState *dev = qdev_create(NULL, TYPE_MIPS_MALTA);
MaltaState *s = MIPS_MALTA(dev);
- /* The whole address space decoded by the GT-64120A doesn't generate
- exception when accessing invalid memory. Create an empty slot to
- emulate this feature. */
+ /*
+ * The whole address space decoded by the GT-64120A doesn't generate
+ * exception when accessing invalid memory. Create an empty slot to
+ * emulate this feature.\
+ */
empty_slot_init(0, 0x20000000);
qdev_init_nofail(dev);
@@ -1331,8 +1367,10 @@ void mips_malta_init(MachineState *machine)
exit(1);
}
}
- /* In little endian mode the 32bit words in the bios are swapped,
- a neat trick which allows bi-endian firmware. */
+ /*
+ * In little endian mode the 32bit words in the bios are swapped,
+ * a neat trick which allows bi-endian firmware.
+ */
#ifndef TARGET_WORDS_BIGENDIAN
{
uint32_t *end, *addr;
@@ -1386,8 +1424,10 @@ void mips_malta_init(MachineState *machine)
piix4_devfn = piix4_init(pci_bus, &isa_bus, 80);
- /* Interrupt controller */
- /* The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2 */
+ /*
+ * Interrupt controller
+ * The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2
+ */
s->i8259 = i8259_init(isa_bus, i8259_irq);
isa_bus_irqs(isa_bus, s->i8259);
diff --git a/hw/mips/mips_mipssim.c b/hw/mips/mips_mipssim.c
index 1ca7e90..282bbec 100644
--- a/hw/mips/mips_mipssim.c
+++ b/hw/mips/mips_mipssim.c
@@ -3,7 +3,7 @@
*
* Emulates a very simple machine model similar to the one used by the
* proprietary MIPS emulator.
- *
+ *
* Copyright (c) 2007 Thiemo Seufer
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
@@ -76,8 +76,9 @@ static int64_t load_kernel(void)
(uint64_t *)&kernel_high, big_endian,
EM_MIPS, 1, 0);
if (kernel_size >= 0) {
- if ((entry & ~0x7fffffffULL) == 0x80000000)
+ if ((entry & ~0x7fffffffULL) == 0x80000000) {
entry = (int32_t)entry;
+ }
} else {
error_report("could not load kernel '%s': %s",
loaderparams.kernel_filename,
@@ -89,9 +90,10 @@ static int64_t load_kernel(void)
initrd_size = 0;
initrd_offset = 0;
if (loaderparams.initrd_filename) {
- initrd_size = get_image_size (loaderparams.initrd_filename);
+ initrd_size = get_image_size(loaderparams.initrd_filename);
if (initrd_size > 0) {
- initrd_offset = (kernel_high + ~INITRD_PAGE_MASK) & INITRD_PAGE_MASK;
+ initrd_offset = (kernel_high + ~INITRD_PAGE_MASK) &
+ INITRD_PAGE_MASK;
if (initrd_offset + initrd_size > loaderparams.ram_size) {
error_report("memory too small for initial ram disk '%s'",
loaderparams.initrd_filename);
@@ -175,8 +177,9 @@ mips_mipssim_init(MachineState *machine)
/* Map the BIOS / boot exception handler. */
memory_region_add_subregion(address_space_mem, 0x1fc00000LL, bios);
/* Load a BIOS / boot exception handler image. */
- if (bios_name == NULL)
+ if (bios_name == NULL) {
bios_name = BIOS_FILENAME;
+ }
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (filename) {
bios_size = load_image_targphys(filename, 0x1fc00000LL, BIOS_SIZE);
@@ -212,8 +215,10 @@ mips_mipssim_init(MachineState *machine)
get_system_io(), 0, 0x00010000);
memory_region_add_subregion(get_system_memory(), 0x1fd00000, isa);
- /* A single 16450 sits at offset 0x3f8. It is attached to
- MIPS CPU INT2, which is interrupt 4. */
+ /*
+ * A single 16450 sits at offset 0x3f8. It is attached to
+ * MIPS CPU INT2, which is interrupt 4.
+ */
if (serial_hd(0))
serial_init(0x3f8, env->irq[4], 115200, serial_hd(0),
get_system_io());
generated by cgit v1.1 at 2025-01-01 15:10:18 +0000