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-rw-r--r--hw/bonito.c4
-rw-r--r--hw/gt64xxx.c6
-rw-r--r--hw/isa.h2
-rw-r--r--hw/isa_mmio.c102
-rw-r--r--hw/mips_jazz.c7
-rw-r--r--hw/mips_mipssim.c6
-rw-r--r--hw/mips_r4k.c6
-rw-r--r--hw/ppc440.c2
-rw-r--r--hw/ppc_newworld.c2
-rw-r--r--hw/ppc_oldworld.c2
-rw-r--r--hw/ppce500_mpc8544ds.c2
-rw-r--r--hw/sh_pci.c4
-rw-r--r--hw/sun4u.c4
-rw-r--r--hw/versatile_pci.c6
14 files changed, 36 insertions, 119 deletions
diff --git a/hw/bonito.c b/hw/bonito.c
index fd90527..65a4a63 100644
--- a/hw/bonito.c
+++ b/hw/bonito.c
@@ -743,12 +743,12 @@ static int bonito_initfn(PCIDevice *dev)
s->bonito_pciio_start = BONITO_PCIIO_BASE;
s->bonito_pciio_length = BONITO_PCIIO_SIZE;
isa_mem_base = s->bonito_pciio_start;
- isa_mmio_init(s->bonito_pciio_start, s->bonito_pciio_length, 0);
+ isa_mmio_init(s->bonito_pciio_start, s->bonito_pciio_length);
/* add pci local io mapping */
s->bonito_localio_start = BONITO_DEV_BASE;
s->bonito_localio_length = BONITO_DEV_SIZE;
- isa_mmio_init(s->bonito_localio_start, s->bonito_localio_length, 0);
+ isa_mmio_init(s->bonito_localio_start, s->bonito_localio_length);
/* set the default value of north bridge pci config */
pci_set_word(dev->config + PCI_COMMAND, 0x0000);
diff --git a/hw/gt64xxx.c b/hw/gt64xxx.c
index 51e4db0..14c6ad3 100644
--- a/hw/gt64xxx.c
+++ b/hw/gt64xxx.c
@@ -297,11 +297,7 @@ static void gt64120_pci_mapping(GT64120State *s)
s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI0IOLD] & 0x7f)) << 21;
isa_mem_base = s->PCI0IO_start;
-#ifdef TARGET_WORDS_BIGENDIAN
- isa_mmio_init(s->PCI0IO_start, s->PCI0IO_length, 1);
-#else
- isa_mmio_init(s->PCI0IO_start, s->PCI0IO_length, 0);
-#endif
+ isa_mmio_init(s->PCI0IO_start, s->PCI0IO_length);
}
}
diff --git a/hw/isa.h b/hw/isa.h
index aaf0272..e6848e4 100644
--- a/hw/isa.h
+++ b/hw/isa.h
@@ -32,7 +32,7 @@ ISADevice *isa_create_simple(const char *name);
extern target_phys_addr_t isa_mem_base;
-void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size, int be);
+void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
/* dma.c */
int DMA_get_channel_mode (int nchan);
diff --git a/hw/isa_mmio.c b/hw/isa_mmio.c
index 46458f4..ca957fb 100644
--- a/hw/isa_mmio.c
+++ b/hw/isa_mmio.c
@@ -31,27 +31,13 @@ static void isa_mmio_writeb (void *opaque, target_phys_addr_t addr,
cpu_outb(addr & IOPORTS_MASK, val);
}
-static void isa_mmio_writew_be(void *opaque, target_phys_addr_t addr,
+static void isa_mmio_writew(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
- val = bswap16(val);
cpu_outw(addr & IOPORTS_MASK, val);
}
-static void isa_mmio_writew_le(void *opaque, target_phys_addr_t addr,
- uint32_t val)
-{
- cpu_outw(addr & IOPORTS_MASK, val);
-}
-
-static void isa_mmio_writel_be(void *opaque, target_phys_addr_t addr,
- uint32_t val)
-{
- val = bswap32(val);
- cpu_outl(addr & IOPORTS_MASK, val);
-}
-
-static void isa_mmio_writel_le(void *opaque, target_phys_addr_t addr,
+static void isa_mmio_writel(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
cpu_outl(addr & IOPORTS_MASK, val);
@@ -59,86 +45,38 @@ static void isa_mmio_writel_le(void *opaque, target_phys_addr_t addr,
static uint32_t isa_mmio_readb (void *opaque, target_phys_addr_t addr)
{
- uint32_t val;
-
- val = cpu_inb(addr & IOPORTS_MASK);
- return val;
+ return cpu_inb(addr & IOPORTS_MASK);
}
-static uint32_t isa_mmio_readw_be(void *opaque, target_phys_addr_t addr)
+static uint32_t isa_mmio_readw(void *opaque, target_phys_addr_t addr)
{
- uint32_t val;
-
- val = cpu_inw(addr & IOPORTS_MASK);
- val = bswap16(val);
- return val;
+ return cpu_inw(addr & IOPORTS_MASK);
}
-static uint32_t isa_mmio_readw_le(void *opaque, target_phys_addr_t addr)
+static uint32_t isa_mmio_readl(void *opaque, target_phys_addr_t addr)
{
- uint32_t val;
-
- val = cpu_inw(addr & IOPORTS_MASK);
- return val;
+ return cpu_inl(addr & IOPORTS_MASK);
}
-static uint32_t isa_mmio_readl_be(void *opaque, target_phys_addr_t addr)
-{
- uint32_t val;
-
- val = cpu_inl(addr & IOPORTS_MASK);
- val = bswap32(val);
- return val;
-}
-
-static uint32_t isa_mmio_readl_le(void *opaque, target_phys_addr_t addr)
-{
- uint32_t val;
-
- val = cpu_inl(addr & IOPORTS_MASK);
- return val;
-}
-
-static CPUWriteMemoryFunc * const isa_mmio_write_be[] = {
- &isa_mmio_writeb,
- &isa_mmio_writew_be,
- &isa_mmio_writel_be,
-};
-
-static CPUReadMemoryFunc * const isa_mmio_read_be[] = {
- &isa_mmio_readb,
- &isa_mmio_readw_be,
- &isa_mmio_readl_be,
-};
-
-static CPUWriteMemoryFunc * const isa_mmio_write_le[] = {
+static CPUWriteMemoryFunc * const isa_mmio_write[] = {
&isa_mmio_writeb,
- &isa_mmio_writew_le,
- &isa_mmio_writel_le,
+ &isa_mmio_writew,
+ &isa_mmio_writel,
};
-static CPUReadMemoryFunc * const isa_mmio_read_le[] = {
+static CPUReadMemoryFunc * const isa_mmio_read[] = {
&isa_mmio_readb,
- &isa_mmio_readw_le,
- &isa_mmio_readl_le,
+ &isa_mmio_readw,
+ &isa_mmio_readl,
};
-static int isa_mmio_iomemtype = 0;
-
-void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size, int be)
+void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size)
{
- if (!isa_mmio_iomemtype) {
- if (be) {
- isa_mmio_iomemtype = cpu_register_io_memory(isa_mmio_read_be,
- isa_mmio_write_be,
- NULL,
- DEVICE_NATIVE_ENDIAN);
- } else {
- isa_mmio_iomemtype = cpu_register_io_memory(isa_mmio_read_le,
- isa_mmio_write_le,
- NULL,
- DEVICE_NATIVE_ENDIAN);
- }
- }
+ int isa_mmio_iomemtype;
+
+ isa_mmio_iomemtype = cpu_register_io_memory(isa_mmio_read,
+ isa_mmio_write,
+ NULL,
+ DEVICE_LITTLE_ENDIAN);
cpu_register_physical_memory(base, size, isa_mmio_iomemtype);
}
diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c
index 1264743..a7caa3f 100644
--- a/hw/mips_jazz.c
+++ b/hw/mips_jazz.c
@@ -205,12 +205,7 @@ void mips_jazz_init (ram_addr_t ram_size,
pcspk_init(pit);
/* ISA IO space at 0x90000000 */
-#ifdef TARGET_WORDS_BIGENDIAN
- isa_mmio_init(0x90000000, 0x01000000, 1);
-#else
- isa_mmio_init(0x90000000, 0x01000000, 0);
-#endif
-
+ isa_mmio_init(0x90000000, 0x01000000);
isa_mem_base = 0x11000000;
/* Video card */
diff --git a/hw/mips_mipssim.c b/hw/mips_mipssim.c
index 111c759..380a7eb 100644
--- a/hw/mips_mipssim.c
+++ b/hw/mips_mipssim.c
@@ -186,11 +186,7 @@ mips_mipssim_init (ram_addr_t ram_size,
cpu_mips_clock_init(env);
/* Register 64 KB of ISA IO space at 0x1fd00000. */
-#ifdef TARGET_WORDS_BIGENDIAN
- isa_mmio_init(0x1fd00000, 0x00010000, 1);
-#else
- isa_mmio_init(0x1fd00000, 0x00010000, 0);
-#endif
+ isa_mmio_init(0x1fd00000, 0x00010000);
/* A single 16450 sits at offset 0x3f8. It is attached to
MIPS CPU INT2, which is interrupt 4. */
diff --git a/hw/mips_r4k.c b/hw/mips_r4k.c
index afe52f3..fb34dcf 100644
--- a/hw/mips_r4k.c
+++ b/hw/mips_r4k.c
@@ -271,11 +271,7 @@ void mips_r4k_init (ram_addr_t ram_size,
rtc_init(2000, NULL);
/* Register 64 KB of ISA IO space at 0x14000000 */
-#ifdef TARGET_WORDS_BIGENDIAN
- isa_mmio_init(0x14000000, 0x00010000, 1);
-#else
- isa_mmio_init(0x14000000, 0x00010000, 0);
-#endif
+ isa_mmio_init(0x14000000, 0x00010000);
isa_mem_base = 0x10000000;
pit = pit_init(0x40, i8259[0]);
diff --git a/hw/ppc440.c b/hw/ppc440.c
index d12cf71..1ed001a 100644
--- a/hw/ppc440.c
+++ b/hw/ppc440.c
@@ -85,7 +85,7 @@ CPUState *ppc440ep_init(ram_addr_t *ram_size, PCIBus **pcip,
if (!*pcip)
printf("couldn't create PCI controller!\n");
- isa_mmio_init(PPC440EP_PCI_IO, PPC440EP_PCI_IOLEN, 1);
+ isa_mmio_init(PPC440EP_PCI_IO, PPC440EP_PCI_IOLEN);
if (serial_hds[0] != NULL) {
serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE,
diff --git a/hw/ppc_newworld.c b/hw/ppc_newworld.c
index 49b046b..b9245f0 100644
--- a/hw/ppc_newworld.c
+++ b/hw/ppc_newworld.c
@@ -257,7 +257,7 @@ static void ppc_core99_init (ram_addr_t ram_size,
isa_mem_base = 0x80000000;
/* Register 8 MB of ISA IO space */
- isa_mmio_init(0xf2000000, 0x00800000, 1);
+ isa_mmio_init(0xf2000000, 0x00800000);
/* UniN init */
unin_memory = cpu_register_io_memory(unin_read, unin_write, NULL,
diff --git a/hw/ppc_oldworld.c b/hw/ppc_oldworld.c
index 5efc93d..8a4e088 100644
--- a/hw/ppc_oldworld.c
+++ b/hw/ppc_oldworld.c
@@ -202,7 +202,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size,
isa_mem_base = 0x80000000;
/* Register 2 MB of ISA IO space */
- isa_mmio_init(0xfe000000, 0x00200000, 1);
+ isa_mmio_init(0xfe000000, 0x00200000);
/* XXX: we register only 1 output pin for heathrow PIC */
heathrow_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
diff --git a/hw/ppce500_mpc8544ds.c b/hw/ppce500_mpc8544ds.c
index 59d20d3..b7670ae 100644
--- a/hw/ppce500_mpc8544ds.c
+++ b/hw/ppce500_mpc8544ds.c
@@ -220,7 +220,7 @@ static void mpc8544ds_init(ram_addr_t ram_size,
if (!pci_bus)
printf("couldn't create PCI controller!\n");
- isa_mmio_init(MPC8544_PCI_IO, MPC8544_PCI_IOLEN, 1);
+ isa_mmio_init(MPC8544_PCI_IO, MPC8544_PCI_IOLEN);
if (pci_bus) {
/* Register network interfaces. */
diff --git a/hw/sh_pci.c b/hw/sh_pci.c
index 6042d9c..072078b 100644
--- a/hw/sh_pci.c
+++ b/hw/sh_pci.c
@@ -54,7 +54,7 @@ static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val)
cpu_register_physical_memory(pcic->iobr & 0xfffc0000, 0x40000,
IO_MEM_UNASSIGNED);
pcic->iobr = val & 0xfffc0001;
- isa_mmio_init(pcic->iobr & 0xfffc0000, 0x40000, 0);
+ isa_mmio_init(pcic->iobr & 0xfffc0000, 0x40000);
}
break;
case 0x220:
@@ -109,7 +109,7 @@ PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
cpu_register_physical_memory(0xfe200000, 0x224, reg);
p->iobr = 0xfe240000;
- isa_mmio_init(p->iobr, 0x40000, 0);
+ isa_mmio_init(p->iobr, 0x40000);
pci_config_set_vendor_id(p->dev->config, PCI_VENDOR_ID_HITACHI);
pci_config_set_device_id(p->dev->config, PCI_DEVICE_ID_HITACHI_SH7751R);
diff --git a/hw/sun4u.c b/hw/sun4u.c
index 5292ac6..90b1ce2 100644
--- a/hw/sun4u.c
+++ b/hw/sun4u.c
@@ -525,10 +525,10 @@ static void ebus_mmio_mapfunc(PCIDevice *pci_dev, int region_num,
region_num, addr);
switch (region_num) {
case 0:
- isa_mmio_init(addr, 0x1000000, 1);
+ isa_mmio_init(addr, 0x1000000);
break;
case 1:
- isa_mmio_init(addr, 0x800000, 1);
+ isa_mmio_init(addr, 0x800000);
break;
}
}
diff --git a/hw/versatile_pci.c b/hw/versatile_pci.c
index cc8f9f8..2fed8a0 100644
--- a/hw/versatile_pci.c
+++ b/hw/versatile_pci.c
@@ -96,11 +96,7 @@ static void pci_vpb_map(SysBusDevice *dev, target_phys_addr_t base)
if (s->realview) {
/* IO memory area. */
-#ifdef TARGET_WORDS_BIGENDIAN
- isa_mmio_init(base + 0x03000000, 0x00100000, 1);
-#else
- isa_mmio_init(base + 0x03000000, 0x00100000, 0);
-#endif
+ isa_mmio_init(base + 0x03000000, 0x00100000);
}
}
generated by cgit v1.1 at 2024-12-29 09:44:53 +0000