diff options
Diffstat (limited to 'hw')
-rw-r--r-- | hw/acpi/piix4.c | 12 | ||||
-rw-r--r-- | hw/char/serial.c | 128 | ||||
-rw-r--r-- | hw/intc/xilinx_intc.c | 6 | ||||
-rw-r--r-- | hw/misc/ivshmem.c | 1 | ||||
-rw-r--r-- | hw/scsi/vmw_pvscsi.c | 2 | ||||
-rw-r--r-- | hw/xen/xen_pt_config_init.c | 4 |
6 files changed, 62 insertions, 91 deletions
diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index e6525ac..756df3b 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -518,7 +518,7 @@ static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width) PIIX4PMState *s = opaque; uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); - PIIX4_DPRINTF("gpe read %x == %x\n", addr, val); + PIIX4_DPRINTF("gpe read %" HWADDR_PRIx " == %" PRIu32 "\n", addr, val); return val; } @@ -530,7 +530,7 @@ static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val, acpi_gpe_ioport_writeb(&s->ar, addr, val); pm_update_sci(s); - PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val); + PIIX4_DPRINTF("gpe write %" HWADDR_PRIx " <== %" PRIu64 "\n", addr, val); } static const MemoryRegionOps piix4_gpe_ops = { @@ -553,15 +553,15 @@ static uint64_t pci_read(void *opaque, hwaddr addr, unsigned int size) /* Manufacture an "up" value to cause a device check on any hotplug * slot with a device. Extra device checks are harmless. */ val = s->pci0_slot_device_present & s->pci0_hotplug_enable; - PIIX4_DPRINTF("pci_up_read %x\n", val); + PIIX4_DPRINTF("pci_up_read %" PRIu32 "\n", val); break; case PCI_DOWN_BASE - PCI_HOTPLUG_ADDR: val = s->pci0_status.down; - PIIX4_DPRINTF("pci_down_read %x\n", val); + PIIX4_DPRINTF("pci_down_read %" PRIu32 "\n", val); break; case PCI_EJ_BASE - PCI_HOTPLUG_ADDR: /* No feature defined yet */ - PIIX4_DPRINTF("pci_features_read %x\n", val); + PIIX4_DPRINTF("pci_features_read %" PRIu32 "\n", val); break; case PCI_RMV_BASE - PCI_HOTPLUG_ADDR: val = s->pci0_hotplug_enable; @@ -579,7 +579,7 @@ static void pci_write(void *opaque, hwaddr addr, uint64_t data, switch (addr) { case PCI_EJ_BASE - PCI_HOTPLUG_ADDR: acpi_piix_eject_slot(opaque, (uint32_t)data); - PIIX4_DPRINTF("pciej write %" HWADDR_PRIx " <== % " PRIu64 "\n", + PIIX4_DPRINTF("pciej write %" HWADDR_PRIx " <== %" PRIu64 "\n", addr, data); break; default: diff --git a/hw/char/serial.c b/hw/char/serial.c index 66b6348..017610e 100644 --- a/hw/char/serial.c +++ b/hw/char/serial.c @@ -92,8 +92,6 @@ #define UART_FCR_RFR 0x02 /* RCVR Fifo Reset */ #define UART_FCR_FE 0x01 /* FIFO Enable */ -#define XMIT_FIFO 0 -#define RECV_FIFO 1 #define MAX_XMIT_RETRY 4 #ifdef DEBUG_SERIAL @@ -106,50 +104,14 @@ do {} while (0) static void serial_receive1(void *opaque, const uint8_t *buf, int size); -static void fifo_clear(SerialState *s, int fifo) +static inline void recv_fifo_put(SerialState *s, uint8_t chr) { - SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo; - memset(f->data, 0, UART_FIFO_LENGTH); - f->count = 0; - f->head = 0; - f->tail = 0; -} - -static int fifo_put(SerialState *s, int fifo, uint8_t chr) -{ - SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo; - /* Receive overruns do not overwrite FIFO contents. */ - if (fifo == XMIT_FIFO || f->count < UART_FIFO_LENGTH) { - - f->data[f->head++] = chr; - - if (f->head == UART_FIFO_LENGTH) - f->head = 0; - } - - if (f->count < UART_FIFO_LENGTH) - f->count++; - else if (fifo == RECV_FIFO) + if (!fifo8_is_full(&s->recv_fifo)) { + fifo8_push(&s->recv_fifo, chr); + } else { s->lsr |= UART_LSR_OE; - - return 1; -} - -static uint8_t fifo_get(SerialState *s, int fifo) -{ - SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo; - uint8_t c; - - if(f->count == 0) - return 0; - - c = f->data[f->tail++]; - if (f->tail == UART_FIFO_LENGTH) - f->tail = 0; - f->count--; - - return c; + } } static void serial_update_irq(SerialState *s) @@ -165,7 +127,7 @@ static void serial_update_irq(SerialState *s) tmp_iir = UART_IIR_CTI; } else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR) && (!(s->fcr & UART_FCR_FE) || - s->recv_fifo.count >= s->recv_fifo.itl)) { + s->recv_fifo.num >= s->recv_fifo_itl)) { tmp_iir = UART_IIR_RDI; } else if ((s->ier & UART_IER_THRI) && s->thr_ipending) { tmp_iir = UART_IIR_THRI; @@ -262,9 +224,11 @@ static gboolean serial_xmit(GIOChannel *chan, GIOCondition cond, void *opaque) if (s->tsr_retry <= 0) { if (s->fcr & UART_FCR_FE) { - s->tsr = fifo_get(s,XMIT_FIFO); - if (!s->xmit_fifo.count) + s->tsr = fifo8_is_full(&s->xmit_fifo) ? + 0 : fifo8_pop(&s->xmit_fifo); + if (!s->xmit_fifo.num) { s->lsr |= UART_LSR_THRE; + } } else if ((s->lsr & UART_LSR_THRE)) { return FALSE; } else { @@ -316,16 +280,16 @@ static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val, } else { s->thr = (uint8_t) val; if(s->fcr & UART_FCR_FE) { - fifo_put(s, XMIT_FIFO, s->thr); - s->thr_ipending = 0; + /* xmit overruns overwrite data, so make space if needed */ + if (fifo8_is_full(&s->xmit_fifo)) { + fifo8_pop(&s->xmit_fifo); + } + fifo8_push(&s->xmit_fifo, s->thr); s->lsr &= ~UART_LSR_TEMT; - s->lsr &= ~UART_LSR_THRE; - serial_update_irq(s); - } else { - s->thr_ipending = 0; - s->lsr &= ~UART_LSR_THRE; - serial_update_irq(s); } + s->thr_ipending = 0; + s->lsr &= ~UART_LSR_THRE; + serial_update_irq(s); serial_xmit(NULL, G_IO_OUT, s); } break; @@ -367,28 +331,28 @@ static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val, if (val & UART_FCR_RFR) { qemu_del_timer(s->fifo_timeout_timer); s->timeout_ipending=0; - fifo_clear(s,RECV_FIFO); + fifo8_reset(&s->recv_fifo); } if (val & UART_FCR_XFR) { - fifo_clear(s,XMIT_FIFO); + fifo8_reset(&s->xmit_fifo); } if (val & UART_FCR_FE) { s->iir |= UART_IIR_FE; - /* Set RECV_FIFO trigger Level */ + /* Set recv_fifo trigger Level */ switch (val & 0xC0) { case UART_FCR_ITL_1: - s->recv_fifo.itl = 1; + s->recv_fifo_itl = 1; break; case UART_FCR_ITL_2: - s->recv_fifo.itl = 4; + s->recv_fifo_itl = 4; break; case UART_FCR_ITL_3: - s->recv_fifo.itl = 8; + s->recv_fifo_itl = 8; break; case UART_FCR_ITL_4: - s->recv_fifo.itl = 14; + s->recv_fifo_itl = 14; break; } } else @@ -460,11 +424,13 @@ static uint64_t serial_ioport_read(void *opaque, hwaddr addr, unsigned size) ret = s->divider & 0xff; } else { if(s->fcr & UART_FCR_FE) { - ret = fifo_get(s,RECV_FIFO); - if (s->recv_fifo.count == 0) + ret = fifo8_is_full(&s->recv_fifo) ? + 0 : fifo8_pop(&s->recv_fifo); + if (s->recv_fifo.num == 0) { s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); - else + } else { qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock_ns (vm_clock) + s->char_transmit_time * 4); + } s->timeout_ipending = 0; } else { ret = s->rbr; @@ -534,15 +500,21 @@ static uint64_t serial_ioport_read(void *opaque, hwaddr addr, unsigned size) static int serial_can_receive(SerialState *s) { if(s->fcr & UART_FCR_FE) { - if(s->recv_fifo.count < UART_FIFO_LENGTH) - /* Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1 if above. If UART_FIFO_LENGTH - fifo.count is - advertised the effect will be to almost always fill the fifo completely before the guest has a chance to respond, - effectively overriding the ITL that the guest has set. */ - return (s->recv_fifo.count <= s->recv_fifo.itl) ? s->recv_fifo.itl - s->recv_fifo.count : 1; - else - return 0; + if (s->recv_fifo.num < UART_FIFO_LENGTH) { + /* + * Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1 + * if above. If UART_FIFO_LENGTH - fifo.count is advertised the + * effect will be to almost always fill the fifo completely before + * the guest has a chance to respond, effectively overriding the ITL + * that the guest has set. + */ + return (s->recv_fifo.num <= s->recv_fifo_itl) ? + s->recv_fifo_itl - s->recv_fifo.num : 1; + } else { + return 0; + } } else { - return !(s->lsr & UART_LSR_DR); + return !(s->lsr & UART_LSR_DR); } } @@ -550,7 +522,7 @@ static void serial_receive_break(SerialState *s) { s->rbr = 0; /* When the LSR_DR is set a null byte is pushed into the fifo */ - fifo_put(s, RECV_FIFO, '\0'); + recv_fifo_put(s, '\0'); s->lsr |= UART_LSR_BI | UART_LSR_DR; serial_update_irq(s); } @@ -558,7 +530,7 @@ static void serial_receive_break(SerialState *s) /* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */ static void fifo_timeout_int (void *opaque) { SerialState *s = opaque; - if (s->recv_fifo.count) { + if (s->recv_fifo.num) { s->timeout_ipending = 1; serial_update_irq(s); } @@ -580,7 +552,7 @@ static void serial_receive1(void *opaque, const uint8_t *buf, int size) if(s->fcr & UART_FCR_FE) { int i; for (i = 0; i < size; i++) { - fifo_put(s, RECV_FIFO, buf[i]); + recv_fifo_put(s, buf[i]); } s->lsr |= UART_LSR_DR; /* call the timeout receive callback in 4 char transmit time */ @@ -660,8 +632,8 @@ static void serial_reset(void *opaque) s->char_transmit_time = (get_ticks_per_sec() / 9600) * 10; s->poll_msl = 0; - fifo_clear(s,RECV_FIFO); - fifo_clear(s,XMIT_FIFO); + fifo8_reset(&s->recv_fifo); + fifo8_reset(&s->xmit_fifo); s->last_xmit_ts = qemu_get_clock_ns(vm_clock); @@ -684,6 +656,8 @@ void serial_init_core(SerialState *s) qemu_chr_add_handlers(s->chr, serial_can_receive1, serial_receive1, serial_event, s); + fifo8_create(&s->recv_fifo, UART_FIFO_LENGTH); + fifo8_create(&s->xmit_fifo, UART_FIFO_LENGTH); } void serial_exit_core(SerialState *s) diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c index b106e72..5df7008 100644 --- a/hw/intc/xilinx_intc.c +++ b/hw/intc/xilinx_intc.c @@ -66,11 +66,7 @@ static void update_irq(struct xlx_pic *p) i = ~0; p->regs[R_IVR] = i; - if ((p->regs[R_MER] & 1) && p->regs[R_IPR]) { - qemu_irq_raise(p->parent_irq); - } else { - qemu_irq_lower(p->parent_irq); - } + qemu_set_irq(p->parent_irq, (p->regs[R_MER] & 1) && p->regs[R_IPR]); } static uint64_t diff --git a/hw/misc/ivshmem.c b/hw/misc/ivshmem.c index a19a6d6..5658f73 100644 --- a/hw/misc/ivshmem.c +++ b/hw/misc/ivshmem.c @@ -735,6 +735,7 @@ static int pci_ivshmem_init(PCIDevice *dev) if (s->shmobj == NULL) { fprintf(stderr, "Must specify 'chardev' or 'shm' to ivshmem\n"); + exit(1); } IVSHMEM_DPRINTF("using shm_open (shm object = %s)\n", s->shmobj); diff --git a/hw/scsi/vmw_pvscsi.c b/hw/scsi/vmw_pvscsi.c index 48d12f4..446f723 100644 --- a/hw/scsi/vmw_pvscsi.c +++ b/hw/scsi/vmw_pvscsi.c @@ -389,7 +389,7 @@ pvscsi_process_completion_queue(void *opaque) QTAILQ_REMOVE(&s->completion_queue, pvscsi_req, next); pvscsi_cmp_ring_put(s, &pvscsi_req->cmp); g_free(pvscsi_req); - has_completed++; + has_completed = true; } if (has_completed) { diff --git a/hw/xen/xen_pt_config_init.c b/hw/xen/xen_pt_config_init.c index 01872db..8ccc2e4 100644 --- a/hw/xen/xen_pt_config_init.c +++ b/hw/xen/xen_pt_config_init.c @@ -1777,12 +1777,12 @@ static int xen_pt_config_reg_init(XenPCIPassthroughState *s, rc = reg->init(s, reg_entry->reg, reg_grp->base_offset + reg->offset, &data); if (rc < 0) { - free(reg_entry); + g_free(reg_entry); return rc; } if (data == XEN_PT_INVALID_REG) { /* free unused BAR register entry */ - free(reg_entry); + g_free(reg_entry); return 0; } /* set register value */ |