diff options
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/core/register.c | 16 | ||||
| -rw-r--r-- | hw/intc/ibex_plic.c | 13 | ||||
| -rw-r--r-- | hw/riscv/boot.c | 70 | ||||
| -rw-r--r-- | hw/riscv/microchip_pfsoc.c | 21 | ||||
| -rw-r--r-- | hw/riscv/opentitan.c | 81 | ||||
| -rw-r--r-- | hw/riscv/sifive_u.c | 74 | ||||
| -rw-r--r-- | hw/riscv/spike.c | 52 | ||||
| -rw-r--r-- | hw/riscv/virt.c | 39 |
8 files changed, 229 insertions, 137 deletions
diff --git a/hw/core/register.c b/hw/core/register.c index 3600ef5..d6f8c20 100644 --- a/hw/core/register.c +++ b/hw/core/register.c @@ -80,7 +80,7 @@ void register_write(RegisterInfo *reg, uint64_t val, uint64_t we, if (!ac || !ac->name) { qemu_log_mask(LOG_GUEST_ERROR, "%s: write to undefined device state " - "(written value: %#" PRIx64 ")\n", prefix, val); + "(written value: 0x%" PRIx64 ")\n", prefix, val); return; } @@ -89,14 +89,14 @@ void register_write(RegisterInfo *reg, uint64_t val, uint64_t we, test = (old_val ^ val) & ac->rsvd; if (test) { qemu_log_mask(LOG_GUEST_ERROR, "%s: change of value in reserved bit" - "fields: %#" PRIx64 ")\n", prefix, test); + "fields: 0x%" PRIx64 ")\n", prefix, test); } test = val & ac->unimp; if (test) { qemu_log_mask(LOG_UNIMP, - "%s:%s writing %#" PRIx64 " to unimplemented bits:" \ - " %#" PRIx64 "\n", + "%s:%s writing 0x%" PRIx64 " to unimplemented bits:" \ + " 0x%" PRIx64 "\n", prefix, reg->access->name, val, ac->unimp); } @@ -112,7 +112,7 @@ void register_write(RegisterInfo *reg, uint64_t val, uint64_t we, } if (debug) { - qemu_log("%s:%s: write of value %#" PRIx64 "\n", prefix, ac->name, + qemu_log("%s:%s: write of value 0x%" PRIx64 "\n", prefix, ac->name, new_val); } @@ -150,7 +150,7 @@ uint64_t register_read(RegisterInfo *reg, uint64_t re, const char* prefix, } if (debug) { - qemu_log("%s:%s: read of value %#" PRIx64 "\n", prefix, + qemu_log("%s:%s: read of value 0x%" PRIx64 "\n", prefix, ac->name, ret); } @@ -193,7 +193,7 @@ void register_write_memory(void *opaque, hwaddr addr, if (!reg) { qemu_log_mask(LOG_GUEST_ERROR, "%s: write to unimplemented register " \ - "at address: %#" PRIx64 "\n", reg_array->prefix, addr); + "at address: 0x%" PRIx64 "\n", reg_array->prefix, addr); return; } @@ -222,7 +222,7 @@ uint64_t register_read_memory(void *opaque, hwaddr addr, if (!reg) { qemu_log_mask(LOG_GUEST_ERROR, "%s: read to unimplemented register " \ - "at address: %#" PRIx64 "\n", reg_array->prefix, addr); + "at address: 0x%" PRIx64 "\n", reg_array->prefix, addr); return 0; } diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c index 341c9db..c1b72fc 100644 --- a/hw/intc/ibex_plic.c +++ b/hw/intc/ibex_plic.c @@ -43,16 +43,23 @@ static void ibex_plic_irqs_set_pending(IbexPlicState *s, int irq, bool level) { int pending_num = irq / 32; + if (!level) { + /* + * If the level is low make sure we clear the hidden_pending. + */ + s->hidden_pending[pending_num] &= ~(1 << (irq % 32)); + } + if (s->claimed[pending_num] & 1 << (irq % 32)) { /* * The interrupt has been claimed, but not completed. * The pending bit can't be set. + * Save the pending level for after the interrupt is completed. */ s->hidden_pending[pending_num] |= level << (irq % 32); - return; + } else { + s->pending[pending_num] |= level << (irq % 32); } - - s->pending[pending_num] |= level << (irq % 32); } static bool ibex_plic_irqs_pending(IbexPlicState *s, uint32_t context) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index d62f3dc..83586ae 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -33,24 +33,16 @@ #include <libfdt.h> -#if defined(TARGET_RISCV32) -#define fw_dynamic_info_data(__val) cpu_to_le32(__val) -#else -#define fw_dynamic_info_data(__val) cpu_to_le64(__val) -#endif - -bool riscv_is_32_bit(MachineState *machine) +bool riscv_is_32bit(RISCVHartArrayState harts) { - if (!strncmp(machine->cpu_type, "rv32", 4)) { - return true; - } else { - return false; - } + RISCVCPU hart = harts.harts[0]; + + return riscv_cpu_is_32bit(&hart.env); } -target_ulong riscv_calc_kernel_start_addr(MachineState *machine, +target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState harts, target_ulong firmware_end_addr) { - if (riscv_is_32_bit(machine)) { + if (riscv_is_32bit(harts)) { return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB); } else { return QEMU_ALIGN_UP(firmware_end_addr, 2 * MiB); @@ -218,16 +210,24 @@ uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) return fdt_addr; } -void riscv_rom_copy_firmware_info(hwaddr rom_base, hwaddr rom_size, - uint32_t reset_vec_size, uint64_t kernel_entry) +void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base, + hwaddr rom_size, uint32_t reset_vec_size, + uint64_t kernel_entry) { struct fw_dynamic_info dinfo; size_t dinfo_len; - dinfo.magic = fw_dynamic_info_data(FW_DYNAMIC_INFO_MAGIC_VALUE); - dinfo.version = fw_dynamic_info_data(FW_DYNAMIC_INFO_VERSION); - dinfo.next_mode = fw_dynamic_info_data(FW_DYNAMIC_INFO_NEXT_MODE_S); - dinfo.next_addr = fw_dynamic_info_data(kernel_entry); + if (sizeof(dinfo.magic) == 4) { + dinfo.magic = cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VALUE); + dinfo.version = cpu_to_le32(FW_DYNAMIC_INFO_VERSION); + dinfo.next_mode = cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S); + dinfo.next_addr = cpu_to_le32(kernel_entry); + } else { + dinfo.magic = cpu_to_le64(FW_DYNAMIC_INFO_MAGIC_VALUE); + dinfo.version = cpu_to_le64(FW_DYNAMIC_INFO_VERSION); + dinfo.next_mode = cpu_to_le64(FW_DYNAMIC_INFO_NEXT_MODE_S); + dinfo.next_addr = cpu_to_le64(kernel_entry); + } dinfo.options = 0; dinfo.boot_hart = 0; dinfo_len = sizeof(dinfo); @@ -247,28 +247,25 @@ void riscv_rom_copy_firmware_info(hwaddr rom_base, hwaddr rom_size, &address_space_memory); } -void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base, - hwaddr rom_size, uint64_t kernel_entry, +void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState harts, + hwaddr start_addr, + hwaddr rom_base, hwaddr rom_size, + uint64_t kernel_entry, uint32_t fdt_load_addr, void *fdt) { int i; uint32_t start_addr_hi32 = 0x00000000; - #if defined(TARGET_RISCV64) - start_addr_hi32 = start_addr >> 32; - #endif + if (!riscv_is_32bit(harts)) { + start_addr_hi32 = start_addr >> 32; + } /* reset vector */ uint32_t reset_vec[10] = { 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */ 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */ 0xf1402573, /* csrr a0, mhartid */ -#if defined(TARGET_RISCV32) - 0x0202a583, /* lw a1, 32(t0) */ - 0x0182a283, /* lw t0, 24(t0) */ -#elif defined(TARGET_RISCV64) - 0x0202b583, /* ld a1, 32(t0) */ - 0x0182b283, /* ld t0, 24(t0) */ -#endif + 0, + 0, 0x00028067, /* jr t0 */ start_addr, /* start: .dword */ start_addr_hi32, @@ -276,6 +273,13 @@ void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base, 0x00000000, /* fw_dyn: */ }; + if (riscv_is_32bit(harts)) { + reset_vec[3] = 0x0202a583; /* lw a1, 32(t0) */ + reset_vec[4] = 0x0182a283; /* lw t0, 24(t0) */ + } else { + reset_vec[3] = 0x0202b583; /* ld a1, 32(t0) */ + reset_vec[4] = 0x0182b283; /* ld t0, 24(t0) */ + } /* copy in the reset vector in little_endian byte order */ for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { @@ -283,7 +287,7 @@ void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base, } rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), rom_base, &address_space_memory); - riscv_rom_copy_firmware_info(rom_base, rom_size, sizeof(reset_vec), + riscv_rom_copy_firmware_info(machine, rom_base, rom_size, sizeof(reset_vec), kernel_entry); return; diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 37ac46a..e952b49 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -113,6 +113,8 @@ static const struct MemmapEntry { [MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 }, [MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 }, [MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 }, + [MICROCHIP_PFSOC_SPI0] = { 0x20108000, 0x1000 }, + [MICROCHIP_PFSOC_SPI1] = { 0x20109000, 0x1000 }, [MICROCHIP_PFSOC_I2C1] = { 0x2010b000, 0x1000 }, [MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 }, [MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 }, @@ -121,6 +123,7 @@ static const struct MemmapEntry { [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 }, [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 }, [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 }, + [MICROCHIP_PFSOC_QSPI_XIP] = { 0x21000000, 0x1000000 }, [MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 }, [MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 }, [MICROCHIP_PFSOC_DRAM_LO_ALIAS] = { 0xc0000000, 0x40000000 }, @@ -185,6 +188,7 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1); MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); MemoryRegion *envm_data = g_new(MemoryRegion, 1); + MemoryRegion *qspi_xip_mem = g_new(MemoryRegion, 1); char *plic_hart_config; size_t plic_hart_config_len; NICInfo *nd; @@ -344,6 +348,14 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ), serial_hd(4)); + /* SPI */ + create_unimplemented_device("microchip.pfsoc.spi0", + memmap[MICROCHIP_PFSOC_SPI0].base, + memmap[MICROCHIP_PFSOC_SPI0].size); + create_unimplemented_device("microchip.pfsoc.spi1", + memmap[MICROCHIP_PFSOC_SPI1].base, + memmap[MICROCHIP_PFSOC_SPI1].size); + /* I2C1 */ create_unimplemented_device("microchip.pfsoc.i2c1", memmap[MICROCHIP_PFSOC_I2C1].base, @@ -401,6 +413,15 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) sysbus_realize(SYS_BUS_DEVICE(&s->ioscb), errp); sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0, memmap[MICROCHIP_PFSOC_IOSCB].base); + + /* QSPI Flash */ + memory_region_init_rom(qspi_xip_mem, OBJECT(dev), + "microchip.pfsoc.qspi_xip", + memmap[MICROCHIP_PFSOC_QSPI_XIP].size, + &error_fatal); + memory_region_add_subregion(system_memory, + memmap[MICROCHIP_PFSOC_QSPI_XIP].base, + qspi_xip_mem); } static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data) diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index cc758b7..af34569 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -35,22 +35,33 @@ static const struct MemmapEntry { [IBEX_DEV_ROM] = { 0x00008000, 16 * KiB }, [IBEX_DEV_RAM] = { 0x10000000, 0x10000 }, [IBEX_DEV_FLASH] = { 0x20000000, 0x80000 }, - [IBEX_DEV_UART] = { 0x40000000, 0x10000 }, - [IBEX_DEV_GPIO] = { 0x40010000, 0x10000 }, - [IBEX_DEV_SPI] = { 0x40020000, 0x10000 }, - [IBEX_DEV_FLASH_CTRL] = { 0x40030000, 0x10000 }, - [IBEX_DEV_PINMUX] = { 0x40070000, 0x10000 }, - [IBEX_DEV_RV_TIMER] = { 0x40080000, 0x10000 }, - [IBEX_DEV_PLIC] = { 0x40090000, 0x10000 }, - [IBEX_DEV_PWRMGR] = { 0x400A0000, 0x10000 }, - [IBEX_DEV_RSTMGR] = { 0x400B0000, 0x10000 }, - [IBEX_DEV_CLKMGR] = { 0x400C0000, 0x10000 }, - [IBEX_DEV_AES] = { 0x40110000, 0x10000 }, - [IBEX_DEV_HMAC] = { 0x40120000, 0x10000 }, - [IBEX_DEV_ALERT_HANDLER] = { 0x40130000, 0x10000 }, - [IBEX_DEV_NMI_GEN] = { 0x40140000, 0x10000 }, - [IBEX_DEV_USBDEV] = { 0x40150000, 0x10000 }, - [IBEX_DEV_PADCTRL] = { 0x40160000, 0x10000 } + [IBEX_DEV_UART] = { 0x40000000, 0x1000 }, + [IBEX_DEV_GPIO] = { 0x40040000, 0x1000 }, + [IBEX_DEV_SPI] = { 0x40050000, 0x1000 }, + [IBEX_DEV_I2C] = { 0x40080000, 0x1000 }, + [IBEX_DEV_PATTGEN] = { 0x400e0000, 0x1000 }, + [IBEX_DEV_RV_TIMER] = { 0x40100000, 0x1000 }, + [IBEX_DEV_SENSOR_CTRL] = { 0x40110000, 0x1000 }, + [IBEX_DEV_OTP_CTRL] = { 0x40130000, 0x4000 }, + [IBEX_DEV_PWRMGR] = { 0x40400000, 0x1000 }, + [IBEX_DEV_RSTMGR] = { 0x40410000, 0x1000 }, + [IBEX_DEV_CLKMGR] = { 0x40420000, 0x1000 }, + [IBEX_DEV_PINMUX] = { 0x40460000, 0x1000 }, + [IBEX_DEV_PADCTRL] = { 0x40470000, 0x1000 }, + [IBEX_DEV_USBDEV] = { 0x40500000, 0x1000 }, + [IBEX_DEV_FLASH_CTRL] = { 0x41000000, 0x1000 }, + [IBEX_DEV_PLIC] = { 0x41010000, 0x1000 }, + [IBEX_DEV_AES] = { 0x41100000, 0x1000 }, + [IBEX_DEV_HMAC] = { 0x41110000, 0x1000 }, + [IBEX_DEV_KMAC] = { 0x41120000, 0x1000 }, + [IBEX_DEV_KEYMGR] = { 0x41130000, 0x1000 }, + [IBEX_DEV_CSRNG] = { 0x41150000, 0x1000 }, + [IBEX_DEV_ENTROPY] = { 0x41160000, 0x1000 }, + [IBEX_DEV_EDNO] = { 0x41170000, 0x1000 }, + [IBEX_DEV_EDN1] = { 0x41180000, 0x1000 }, + [IBEX_DEV_ALERT_HANDLER] = { 0x411b0000, 0x1000 }, + [IBEX_DEV_NMI_GEN] = { 0x411c0000, 0x1000 }, + [IBEX_DEV_OTBN] = { 0x411d0000, 0x10000 }, }; static void opentitan_board_init(MachineState *machine) @@ -156,30 +167,52 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size); create_unimplemented_device("riscv.lowrisc.ibex.spi", memmap[IBEX_DEV_SPI].base, memmap[IBEX_DEV_SPI].size); - create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl", - memmap[IBEX_DEV_FLASH_CTRL].base, memmap[IBEX_DEV_FLASH_CTRL].size); + create_unimplemented_device("riscv.lowrisc.ibex.i2c", + memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size); + create_unimplemented_device("riscv.lowrisc.ibex.pattgen", + memmap[IBEX_DEV_PATTGEN].base, memmap[IBEX_DEV_PATTGEN].size); create_unimplemented_device("riscv.lowrisc.ibex.rv_timer", memmap[IBEX_DEV_RV_TIMER].base, memmap[IBEX_DEV_RV_TIMER].size); + create_unimplemented_device("riscv.lowrisc.ibex.sensor_ctrl", + memmap[IBEX_DEV_SENSOR_CTRL].base, memmap[IBEX_DEV_SENSOR_CTRL].size); + create_unimplemented_device("riscv.lowrisc.ibex.otp_ctrl", + memmap[IBEX_DEV_OTP_CTRL].base, memmap[IBEX_DEV_OTP_CTRL].size); create_unimplemented_device("riscv.lowrisc.ibex.pwrmgr", memmap[IBEX_DEV_PWRMGR].base, memmap[IBEX_DEV_PWRMGR].size); create_unimplemented_device("riscv.lowrisc.ibex.rstmgr", memmap[IBEX_DEV_RSTMGR].base, memmap[IBEX_DEV_RSTMGR].size); create_unimplemented_device("riscv.lowrisc.ibex.clkmgr", memmap[IBEX_DEV_CLKMGR].base, memmap[IBEX_DEV_CLKMGR].size); + create_unimplemented_device("riscv.lowrisc.ibex.pinmux", + memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size); + create_unimplemented_device("riscv.lowrisc.ibex.padctrl", + memmap[IBEX_DEV_PADCTRL].base, memmap[IBEX_DEV_PADCTRL].size); + create_unimplemented_device("riscv.lowrisc.ibex.usbdev", + memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size); + create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl", + memmap[IBEX_DEV_FLASH_CTRL].base, memmap[IBEX_DEV_FLASH_CTRL].size); create_unimplemented_device("riscv.lowrisc.ibex.aes", memmap[IBEX_DEV_AES].base, memmap[IBEX_DEV_AES].size); create_unimplemented_device("riscv.lowrisc.ibex.hmac", memmap[IBEX_DEV_HMAC].base, memmap[IBEX_DEV_HMAC].size); - create_unimplemented_device("riscv.lowrisc.ibex.pinmux", - memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size); + create_unimplemented_device("riscv.lowrisc.ibex.kmac", + memmap[IBEX_DEV_KMAC].base, memmap[IBEX_DEV_KMAC].size); + create_unimplemented_device("riscv.lowrisc.ibex.keymgr", + memmap[IBEX_DEV_KEYMGR].base, memmap[IBEX_DEV_KEYMGR].size); + create_unimplemented_device("riscv.lowrisc.ibex.csrng", + memmap[IBEX_DEV_CSRNG].base, memmap[IBEX_DEV_CSRNG].size); + create_unimplemented_device("riscv.lowrisc.ibex.entropy", + memmap[IBEX_DEV_ENTROPY].base, memmap[IBEX_DEV_ENTROPY].size); + create_unimplemented_device("riscv.lowrisc.ibex.edn0", + memmap[IBEX_DEV_EDNO].base, memmap[IBEX_DEV_EDNO].size); + create_unimplemented_device("riscv.lowrisc.ibex.edn1", + memmap[IBEX_DEV_EDN1].base, memmap[IBEX_DEV_EDN1].size); create_unimplemented_device("riscv.lowrisc.ibex.alert_handler", memmap[IBEX_DEV_ALERT_HANDLER].base, memmap[IBEX_DEV_ALERT_HANDLER].size); create_unimplemented_device("riscv.lowrisc.ibex.nmi_gen", memmap[IBEX_DEV_NMI_GEN].base, memmap[IBEX_DEV_NMI_GEN].size); - create_unimplemented_device("riscv.lowrisc.ibex.usbdev", - memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size); - create_unimplemented_device("riscv.lowrisc.ibex.padctrl", - memmap[IBEX_DEV_PADCTRL].base, memmap[IBEX_DEV_PADCTRL].size); + create_unimplemented_device("riscv.lowrisc.ibex.otbn", + memmap[IBEX_DEV_OTBN].base, memmap[IBEX_DEV_OTBN].size); } static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index e7f6dc5..f5c400d 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -60,12 +60,6 @@ #include <libfdt.h> -#if defined(TARGET_RISCV32) -# define BIOS_FILENAME "opensbi-riscv32-generic-fw_dynamic.bin" -#else -# define BIOS_FILENAME "opensbi-riscv64-generic-fw_dynamic.bin" -#endif - static const struct MemmapEntry { hwaddr base; hwaddr size; @@ -93,7 +87,7 @@ static const struct MemmapEntry { #define GEM_REVISION 0x10070109 static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, - uint64_t mem_size, const char *cmdline) + uint64_t mem_size, const char *cmdline, bool is_32_bit) { MachineState *ms = MACHINE(qdev_get_machine()); void *fdt; @@ -176,11 +170,11 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_add_subnode(fdt, nodename); /* cpu 0 is the management hart that does not have mmu */ if (cpu != 0) { -#if defined(TARGET_RISCV32) - qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32"); -#else - qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); -#endif + if (is_32_bit) { + qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32"); + } else { + qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); + } isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]); } else { isa = riscv_isa_string(&s->soc.e_cpus.harts[0]); @@ -386,6 +380,21 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, g_free(nodename); nodename = g_strdup_printf("/soc/serial@%lx", + (long)memmap[SIFIVE_U_DEV_UART1].base); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); + qemu_fdt_setprop_cells(fdt, nodename, "reg", + 0x0, memmap[SIFIVE_U_DEV_UART1].base, + 0x0, memmap[SIFIVE_U_DEV_UART1].size); + qemu_fdt_setprop_cells(fdt, nodename, "clocks", + prci_phandle, PRCI_CLK_TLCLK); + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); + qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART1_IRQ); + + qemu_fdt_setprop_string(fdt, "/aliases", "serial1", nodename); + g_free(nodename); + + nodename = g_strdup_printf("/soc/serial@%lx", (long)memmap[SIFIVE_U_DEV_UART0].base); qemu_fdt_add_subnode(fdt, nodename); qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); @@ -456,7 +465,8 @@ static void sifive_u_machine_init(MachineState *machine) qemu_allocate_irq(sifive_u_machine_reset, NULL, 0)); /* create device tree */ - create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); + create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, + riscv_is_32bit(s->soc.u_cpus)); if (s->start_in_flash) { /* @@ -485,11 +495,18 @@ static void sifive_u_machine_init(MachineState *machine) break; } - firmware_end_addr = riscv_find_and_load_firmware(machine, BIOS_FILENAME, - start_addr, NULL); + if (riscv_is_32bit(s->soc.u_cpus)) { + firmware_end_addr = riscv_find_and_load_firmware(machine, + "opensbi-riscv32-generic-fw_dynamic.bin", + start_addr, NULL); + } else { + firmware_end_addr = riscv_find_and_load_firmware(machine, + "opensbi-riscv64-generic-fw_dynamic.bin", + start_addr, NULL); + } if (machine->kernel_filename) { - kernel_start_addr = riscv_calc_kernel_start_addr(machine, + kernel_start_addr = riscv_calc_kernel_start_addr(s->soc.u_cpus, firmware_end_addr); kernel_entry = riscv_load_kernel(machine->kernel_filename, @@ -516,9 +533,9 @@ static void sifive_u_machine_init(MachineState *machine) /* Compute the fdt load address in dram */ fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base, machine->ram_size, s->fdt); - #if defined(TARGET_RISCV64) - start_addr_hi32 = start_addr >> 32; - #endif + if (!riscv_is_32bit(s->soc.u_cpus)) { + start_addr_hi32 = (uint64_t)start_addr >> 32; + } /* reset vector */ uint32_t reset_vec[11] = { @@ -526,13 +543,8 @@ static void sifive_u_machine_init(MachineState *machine) 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */ 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */ 0xf1402573, /* csrr a0, mhartid */ -#if defined(TARGET_RISCV32) - 0x0202a583, /* lw a1, 32(t0) */ - 0x0182a283, /* lw t0, 24(t0) */ -#elif defined(TARGET_RISCV64) - 0x0202b583, /* ld a1, 32(t0) */ - 0x0182b283, /* ld t0, 24(t0) */ -#endif + 0, + 0, 0x00028067, /* jr t0 */ start_addr, /* start: .dword */ start_addr_hi32, @@ -540,6 +552,14 @@ static void sifive_u_machine_init(MachineState *machine) 0x00000000, /* fw_dyn: */ }; + if (riscv_is_32bit(s->soc.u_cpus)) { + reset_vec[4] = 0x0202a583; /* lw a1, 32(t0) */ + reset_vec[5] = 0x0182a283; /* lw t0, 24(t0) */ + } else { + reset_vec[4] = 0x0202b583; /* ld a1, 32(t0) */ + reset_vec[5] = 0x0182b283; /* ld t0, 24(t0) */ + } + /* copy in the reset vector in little_endian byte order */ for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { @@ -548,7 +568,7 @@ static void sifive_u_machine_init(MachineState *machine) rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory); - riscv_rom_copy_firmware_info(memmap[SIFIVE_U_DEV_MROM].base, + riscv_rom_copy_firmware_info(machine, memmap[SIFIVE_U_DEV_MROM].base, memmap[SIFIVE_U_DEV_MROM].size, sizeof(reset_vec), kernel_entry); } diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index facac6e..e723ca0 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -43,17 +43,6 @@ #include "sysemu/qtest.h" #include "sysemu/sysemu.h" -/* - * Not like other RISC-V machines that use plain binary bios images, - * keeping ELF files here was intentional because BIN files don't work - * for the Spike machine as HTIF emulation depends on ELF parsing. - */ -#if defined(TARGET_RISCV32) -# define BIOS_FILENAME "opensbi-riscv32-generic-fw_dynamic.elf" -#else -# define BIOS_FILENAME "opensbi-riscv64-generic-fw_dynamic.elf" -#endif - static const struct MemmapEntry { hwaddr base; hwaddr size; @@ -64,7 +53,7 @@ static const struct MemmapEntry { }; static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap, - uint64_t mem_size, const char *cmdline) + uint64_t mem_size, const char *cmdline, bool is_32_bit) { void *fdt; uint64_t addr, size; @@ -115,11 +104,11 @@ static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap, cpu_name = g_strdup_printf("/cpus/cpu@%d", s->soc[socket].hartid_base + cpu); qemu_fdt_add_subnode(fdt, cpu_name); -#if defined(TARGET_RISCV32) - qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32"); -#else - qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48"); -#endif + if (is_32_bit) { + qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32"); + } else { + qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48"); + } name = riscv_isa_string(&s->soc[socket].harts[cpu]); qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name); g_free(name); @@ -254,7 +243,8 @@ static void spike_board_init(MachineState *machine) main_mem); /* create device tree */ - create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); + create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, + riscv_is_32bit(s->soc[0])); /* boot rom */ memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom", @@ -262,12 +252,25 @@ static void spike_board_init(MachineState *machine) memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base, mask_rom); - firmware_end_addr = riscv_find_and_load_firmware(machine, BIOS_FILENAME, - memmap[SPIKE_DRAM].base, - htif_symbol_callback); + /* + * Not like other RISC-V machines that use plain binary bios images, + * keeping ELF files here was intentional because BIN files don't work + * for the Spike machine as HTIF emulation depends on ELF parsing. + */ + if (riscv_is_32bit(s->soc[0])) { + firmware_end_addr = riscv_find_and_load_firmware(machine, + "opensbi-riscv32-generic-fw_dynamic.elf", + memmap[SPIKE_DRAM].base, + htif_symbol_callback); + } else { + firmware_end_addr = riscv_find_and_load_firmware(machine, + "opensbi-riscv64-generic-fw_dynamic.elf", + memmap[SPIKE_DRAM].base, + htif_symbol_callback); + } if (machine->kernel_filename) { - kernel_start_addr = riscv_calc_kernel_start_addr(machine, + kernel_start_addr = riscv_calc_kernel_start_addr(s->soc[0], firmware_end_addr); kernel_entry = riscv_load_kernel(machine->kernel_filename, @@ -296,7 +299,8 @@ static void spike_board_init(MachineState *machine) fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base, machine->ram_size, s->fdt); /* load the reset vector */ - riscv_setup_rom_reset_vec(memmap[SPIKE_DRAM].base, memmap[SPIKE_MROM].base, + riscv_setup_rom_reset_vec(machine, s->soc[0], memmap[SPIKE_DRAM].base, + memmap[SPIKE_MROM].base, memmap[SPIKE_MROM].size, kernel_entry, fdt_load_addr, s->fdt); @@ -317,7 +321,7 @@ static void spike_machine_class_init(ObjectClass *oc, void *data) mc->init = spike_board_init; mc->max_cpus = SPIKE_CPUS_MAX; mc->is_default = true; - mc->default_cpu_type = SPIKE_V1_10_0_CPU; + mc->default_cpu_type = TYPE_RISCV_CPU_BASE; mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 3cc18a7..8de4c35 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -43,12 +43,6 @@ #include "hw/pci/pci.h" #include "hw/pci-host/gpex.h" -#if defined(TARGET_RISCV32) -# define BIOS_FILENAME "opensbi-riscv32-generic-fw_dynamic.bin" -#else -# define BIOS_FILENAME "opensbi-riscv64-generic-fw_dynamic.bin" -#endif - static const struct MemmapEntry { hwaddr base; hwaddr size; @@ -177,7 +171,7 @@ static void create_pcie_irq_map(void *fdt, char *nodename, } static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, - uint64_t mem_size, const char *cmdline) + uint64_t mem_size, const char *cmdline, bool is_32_bit) { void *fdt; int i, cpu, socket; @@ -240,11 +234,11 @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, cpu_name = g_strdup_printf("/cpus/cpu@%d", s->soc[socket].hartid_base + cpu); qemu_fdt_add_subnode(fdt, cpu_name); -#if defined(TARGET_RISCV32) - qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32"); -#else - qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48"); -#endif + if (is_32_bit) { + qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32"); + } else { + qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48"); + } name = riscv_isa_string(&s->soc[socket].harts[cpu]); qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name); g_free(name); @@ -606,7 +600,8 @@ static void virt_machine_init(MachineState *machine) main_mem); /* create device tree */ - create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); + create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, + riscv_is_32bit(s->soc[0])); /* boot rom */ memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", @@ -614,11 +609,18 @@ static void virt_machine_init(MachineState *machine) memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, mask_rom); - firmware_end_addr = riscv_find_and_load_firmware(machine, BIOS_FILENAME, - start_addr, NULL); + if (riscv_is_32bit(s->soc[0])) { + firmware_end_addr = riscv_find_and_load_firmware(machine, + "opensbi-riscv32-generic-fw_dynamic.bin", + start_addr, NULL); + } else { + firmware_end_addr = riscv_find_and_load_firmware(machine, + "opensbi-riscv64-generic-fw_dynamic.bin", + start_addr, NULL); + } if (machine->kernel_filename) { - kernel_start_addr = riscv_calc_kernel_start_addr(machine, + kernel_start_addr = riscv_calc_kernel_start_addr(s->soc[0], firmware_end_addr); kernel_entry = riscv_load_kernel(machine->kernel_filename, @@ -654,7 +656,8 @@ static void virt_machine_init(MachineState *machine) fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base, machine->ram_size, s->fdt); /* load the reset vector */ - riscv_setup_rom_reset_vec(start_addr, virt_memmap[VIRT_MROM].base, + riscv_setup_rom_reset_vec(machine, s->soc[0], start_addr, + virt_memmap[VIRT_MROM].base, virt_memmap[VIRT_MROM].size, kernel_entry, fdt_load_addr, s->fdt); @@ -704,7 +707,7 @@ static void virt_machine_class_init(ObjectClass *oc, void *data) mc->desc = "RISC-V VirtIO board"; mc->init = virt_machine_init; mc->max_cpus = VIRT_CPUS_MAX; - mc->default_cpu_type = VIRT_CPU; + mc->default_cpu_type = TYPE_RISCV_CPU_BASE; mc->pci_allow_0_address = true; mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; |