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Diffstat (limited to 'hw/timer/sh_timer.c')
-rw-r--r--hw/timer/sh_timer.c151
1 files changed, 78 insertions, 73 deletions
diff --git a/hw/timer/sh_timer.c b/hw/timer/sh_timer.c
index 58af1a1..c72c327 100644
--- a/hw/timer/sh_timer.c
+++ b/hw/timer/sh_timer.c
@@ -10,13 +10,12 @@
#include "qemu/osdep.h"
#include "exec/memory.h"
-#include "hw/hw.h"
+#include "qemu/log.h"
#include "hw/irq.h"
#include "hw/sh4/sh.h"
#include "hw/timer/tmu012.h"
#include "hw/ptimer.h"
-
-//#define DEBUG_TIMER
+#include "trace.h"
#define TIMER_TCR_TPSC (7 << 0)
#define TIMER_TCR_CKEG (3 << 3)
@@ -46,24 +45,24 @@ typedef struct {
int feat;
int enabled;
qemu_irq irq;
-} sh_timer_state;
+} SHTimerState;
/* Check all active timers, and schedule the next timer interrupt. */
-static void sh_timer_update(sh_timer_state *s)
+static void sh_timer_update(SHTimerState *s)
{
int new_level = s->int_level && (s->tcr & TIMER_TCR_UNIE);
- if (new_level != s->old_level)
- qemu_set_irq (s->irq, new_level);
-
+ if (new_level != s->old_level) {
+ qemu_set_irq(s->irq, new_level);
+ }
s->old_level = s->int_level;
s->int_level = new_level;
}
static uint32_t sh_timer_read(void *opaque, hwaddr offset)
{
- sh_timer_state *s = (sh_timer_state *)opaque;
+ SHTimerState *s = opaque;
switch (offset >> 2) {
case OFFSET_TCOR:
@@ -73,19 +72,18 @@ static uint32_t sh_timer_read(void *opaque, hwaddr offset)
case OFFSET_TCR:
return s->tcr | (s->int_level ? TIMER_TCR_UNF : 0);
case OFFSET_TCPR:
- if (s->feat & TIMER_FEAT_CAPT)
+ if (s->feat & TIMER_FEAT_CAPT) {
return s->tcpr;
- /* fall through */
- default:
- hw_error("sh_timer_read: Bad offset %x\n", (int)offset);
- return 0;
+ }
}
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
+ __func__, offset);
+ return 0;
}
-static void sh_timer_write(void *opaque, hwaddr offset,
- uint32_t value)
+static void sh_timer_write(void *opaque, hwaddr offset, uint32_t value)
{
- sh_timer_state *s = (sh_timer_state *)opaque;
+ SHTimerState *s = opaque;
int freq;
switch (offset >> 2) {
@@ -104,19 +102,30 @@ static void sh_timer_write(void *opaque, hwaddr offset,
case OFFSET_TCR:
ptimer_transaction_begin(s->timer);
if (s->enabled) {
- /* Pause the timer if it is running. This may cause some
- inaccuracy dure to rounding, but avoids a whole lot of other
- messyness. */
+ /*
+ * Pause the timer if it is running. This may cause some inaccuracy
+ * due to rounding, but avoids a whole lot of other messiness
+ */
ptimer_stop(s->timer);
}
freq = s->freq;
/* ??? Need to recalculate expiry time after changing divisor. */
switch (value & TIMER_TCR_TPSC) {
- case 0: freq >>= 2; break;
- case 1: freq >>= 4; break;
- case 2: freq >>= 6; break;
- case 3: freq >>= 8; break;
- case 4: freq >>= 10; break;
+ case 0:
+ freq >>= 2;
+ break;
+ case 1:
+ freq >>= 4;
+ break;
+ case 2:
+ freq >>= 6;
+ break;
+ case 3:
+ freq >>= 8;
+ break;
+ case 4:
+ freq >>= 10;
+ break;
case 6:
case 7:
if (s->feat & TIMER_FEAT_EXTCLK) {
@@ -124,7 +133,8 @@ static void sh_timer_write(void *opaque, hwaddr offset,
}
/* fallthrough */
default:
- hw_error("sh_timer_write: Reserved TPSC value\n");
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Reserved TPSC value\n", __func__);
}
switch ((value & TIMER_TCR_CKEG) >> 3) {
case 0:
@@ -137,7 +147,8 @@ static void sh_timer_write(void *opaque, hwaddr offset,
}
/* fallthrough */
default:
- hw_error("sh_timer_write: Reserved CKEG value\n");
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Reserved CKEG value\n", __func__);
}
switch ((value & TIMER_TCR_ICPE) >> 6) {
case 0:
@@ -149,7 +160,8 @@ static void sh_timer_write(void *opaque, hwaddr offset,
}
/* fallthrough */
default:
- hw_error("sh_timer_write: Reserved ICPE value\n");
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Reserved ICPE value\n", __func__);
}
if ((value & TIMER_TCR_UNF) == 0) {
s->int_level = 0;
@@ -158,13 +170,15 @@ static void sh_timer_write(void *opaque, hwaddr offset,
value &= ~TIMER_TCR_UNF;
if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT))) {
- hw_error("sh_timer_write: Reserved ICPF value\n");
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Reserved ICPF value\n", __func__);
}
value &= ~TIMER_TCR_ICPF; /* capture not supported */
if (value & TIMER_TCR_RESERVED) {
- hw_error("sh_timer_write: Reserved TCR bits set\n");
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Reserved TCR bits set\n", __func__);
}
s->tcr = value;
ptimer_set_limit(s->timer, s->tcor, 0);
@@ -182,19 +196,17 @@ static void sh_timer_write(void *opaque, hwaddr offset,
}
/* fallthrough */
default:
- hw_error("sh_timer_write: Bad offset %x\n", (int)offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset);
}
sh_timer_update(s);
}
static void sh_timer_start_stop(void *opaque, int enable)
{
- sh_timer_state *s = (sh_timer_state *)opaque;
-
-#ifdef DEBUG_TIMER
- printf("sh_timer_start_stop %d (%d)\n", enable, s->enabled);
-#endif
+ SHTimerState *s = opaque;
+ trace_sh_timer_start_stop(enable, s->enabled);
ptimer_transaction_begin(s->timer);
if (s->enabled && !enable) {
ptimer_stop(s->timer);
@@ -204,24 +216,20 @@ static void sh_timer_start_stop(void *opaque, int enable)
}
ptimer_transaction_commit(s->timer);
s->enabled = !!enable;
-
-#ifdef DEBUG_TIMER
- printf("sh_timer_start_stop done %d\n", s->enabled);
-#endif
}
static void sh_timer_tick(void *opaque)
{
- sh_timer_state *s = (sh_timer_state *)opaque;
+ SHTimerState *s = opaque;
s->int_level = s->enabled;
sh_timer_update(s);
}
static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq)
{
- sh_timer_state *s;
+ SHTimerState *s;
- s = (sh_timer_state *)g_malloc0(sizeof(sh_timer_state));
+ s = g_malloc0(sizeof(*s));
s->freq = freq;
s->feat = feat;
s->tcor = 0xffffffff;
@@ -252,50 +260,49 @@ typedef struct {
int feat;
} tmu012_state;
-static uint64_t tmu012_read(void *opaque, hwaddr offset,
- unsigned size)
+static uint64_t tmu012_read(void *opaque, hwaddr offset, unsigned size)
{
- tmu012_state *s = (tmu012_state *)opaque;
-
-#ifdef DEBUG_TIMER
- printf("tmu012_read 0x%lx\n", (unsigned long) offset);
-#endif
+ tmu012_state *s = opaque;
+ trace_sh_timer_read(offset);
if (offset >= 0x20) {
if (!(s->feat & TMU012_FEAT_3CHAN)) {
- hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad channel offset 0x%" HWADDR_PRIx "\n",
+ __func__, offset);
}
return sh_timer_read(s->timer[2], offset - 0x20);
}
- if (offset >= 0x14)
+ if (offset >= 0x14) {
return sh_timer_read(s->timer[1], offset - 0x14);
-
- if (offset >= 0x08)
+ }
+ if (offset >= 0x08) {
return sh_timer_read(s->timer[0], offset - 0x08);
-
- if (offset == 4)
+ }
+ if (offset == 4) {
return s->tstr;
-
- if ((s->feat & TMU012_FEAT_TOCR) && offset == 0)
+ }
+ if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) {
return s->tocr;
+ }
- hw_error("tmu012_write: Bad offset %x\n", (int)offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset);
return 0;
}
static void tmu012_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
- tmu012_state *s = (tmu012_state *)opaque;
-
-#ifdef DEBUG_TIMER
- printf("tmu012_write 0x%lx 0x%08x\n", (unsigned long) offset, value);
-#endif
+ tmu012_state *s = opaque;
+ trace_sh_timer_write(offset, value);
if (offset >= 0x20) {
if (!(s->feat & TMU012_FEAT_3CHAN)) {
- hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad channel offset 0x%" HWADDR_PRIx "\n",
+ __func__, offset);
}
sh_timer_write(s->timer[2], offset - 0x20, value);
return;
@@ -318,7 +325,7 @@ static void tmu012_write(void *opaque, hwaddr offset,
sh_timer_start_stop(s->timer[2], value & (1 << 2));
} else {
if (value & (1 << 2)) {
- hw_error("tmu012_write: Bad channel\n");
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad channel\n", __func__);
}
}
@@ -337,15 +344,14 @@ static const MemoryRegionOps tmu012_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
-void tmu012_init(MemoryRegion *sysmem, hwaddr base,
- int feat, uint32_t freq,
+void tmu012_init(MemoryRegion *sysmem, hwaddr base, int feat, uint32_t freq,
qemu_irq ch0_irq, qemu_irq ch1_irq,
qemu_irq ch2_irq0, qemu_irq ch2_irq1)
{
tmu012_state *s;
int timer_feat = (feat & TMU012_FEAT_EXTCLK) ? TIMER_FEAT_EXTCLK : 0;
- s = (tmu012_state *)g_malloc0(sizeof(tmu012_state));
+ s = g_malloc0(sizeof(*s));
s->feat = feat;
s->timer[0] = sh_timer_init(freq, timer_feat, ch0_irq);
s->timer[1] = sh_timer_init(freq, timer_feat, ch1_irq);
@@ -354,15 +360,14 @@ void tmu012_init(MemoryRegion *sysmem, hwaddr base,
ch2_irq0); /* ch2_irq1 not supported */
}
- memory_region_init_io(&s->iomem, NULL, &tmu012_ops, s,
- "timer", 0x100000000ULL);
+ memory_region_init_io(&s->iomem, NULL, &tmu012_ops, s, "timer", 0x30);
memory_region_init_alias(&s->iomem_p4, NULL, "timer-p4",
- &s->iomem, 0, 0x1000);
+ &s->iomem, 0, memory_region_size(&s->iomem));
memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4);
memory_region_init_alias(&s->iomem_a7, NULL, "timer-a7",
- &s->iomem, 0, 0x1000);
+ &s->iomem, 0, memory_region_size(&s->iomem));
memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7);
/* ??? Save/restore. */
}
generated by cgit v1.1 at 2025-03-19 18:07:04 +0000