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-rw-r--r--hw/mips/mips_mipssim.c15
1 files changed, 12 insertions, 3 deletions
diff --git a/hw/mips/mips_mipssim.c b/hw/mips/mips_mipssim.c
index 282bbec..5ee2610 100644
--- a/hw/mips/mips_mipssim.c
+++ b/hw/mips/mips_mipssim.c
@@ -40,6 +40,7 @@
#include "hw/loader.h"
#include "elf.h"
#include "hw/sysbus.h"
+#include "hw/qdev-properties.h"
#include "exec/address-spaces.h"
#include "qemu/error-report.h"
#include "sysemu/qtest.h"
@@ -219,9 +220,17 @@ mips_mipssim_init(MachineState *machine)
* A single 16450 sits at offset 0x3f8. It is attached to
* MIPS CPU INT2, which is interrupt 4.
*/
- if (serial_hd(0))
- serial_init(0x3f8, env->irq[4], 115200, serial_hd(0),
- get_system_io());
+ if (serial_hd(0)) {
+ DeviceState *dev = qdev_create(NULL, TYPE_SERIAL_IO);
+
+ qdev_prop_set_uint32(dev, "baudbase", 115200);
+ qdev_prop_set_chr(dev, "chardev", serial_hd(0));
+ qdev_set_legacy_instance_id(dev, 0x3f8, 2);
+ qdev_init_nofail(dev);
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, env->irq[4]);
+ memory_region_add_subregion(get_system_io(), 0x3f8,
+ &SERIAL_IO(dev)->serial.io);
+ }
if (nd_table[0].used)
/* MIPSnet uses the MIPS CPU INT0, which is interrupt 2. */