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-rw-r--r--hw/intc/pnv_xive.c415
-rw-r--r--hw/intc/spapr_xive.c102
-rw-r--r--hw/intc/spapr_xive_kvm.c42
-rw-r--r--hw/intc/xics.c59
-rw-r--r--hw/intc/xics_kvm.c24
-rw-r--r--hw/intc/xics_spapr.c5
-rw-r--r--hw/intc/xive.c398
7 files changed, 646 insertions, 399 deletions
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index 348f2fd..a0a69b9 100644
--- a/hw/intc/pnv_xive.c
+++ b/hw/intc/pnv_xive.c
@@ -29,7 +29,7 @@
#include "pnv_xive_regs.h"
-#define XIVE_DEBUG
+#undef XIVE_DEBUG
/*
* Virtual structures table (VST)
@@ -86,12 +86,29 @@ static inline uint64_t SETFIELD(uint64_t mask, uint64_t word,
}
/*
+ * When PC_TCTXT_CHIPID_OVERRIDE is configured, the PC_TCTXT_CHIPID
+ * field overrides the hardwired chip ID in the Powerbus operations
+ * and for CAM compares
+ */
+static uint8_t pnv_xive_block_id(PnvXive *xive)
+{
+ uint8_t blk = xive->chip->chip_id;
+ uint64_t cfg_val = xive->regs[PC_TCTXT_CFG >> 3];
+
+ if (cfg_val & PC_TCTXT_CHIPID_OVERRIDE) {
+ blk = GETFIELD(PC_TCTXT_CHIPID, cfg_val);
+ }
+
+ return blk;
+}
+
+/*
* Remote access to controllers. HW uses MMIOs. For now, a simple scan
* of the chips is good enough.
*
* TODO: Block scope support
*/
-static PnvXive *pnv_xive_get_ic(uint8_t blk)
+static PnvXive *pnv_xive_get_remote(uint8_t blk)
{
PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
int i;
@@ -100,7 +117,7 @@ static PnvXive *pnv_xive_get_ic(uint8_t blk)
Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]);
PnvXive *xive = &chip9->xive;
- if (xive->chip->chip_id == blk) {
+ if (pnv_xive_block_id(xive) == blk) {
return xive;
}
}
@@ -123,36 +140,22 @@ static uint64_t pnv_xive_vst_page_size_allowed(uint32_t page_shift)
page_shift == 21 || page_shift == 24;
}
-static uint64_t pnv_xive_vst_size(uint64_t vsd)
-{
- uint64_t vst_tsize = 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12);
-
- /*
- * Read the first descriptor to get the page size of the indirect
- * table.
- */
- if (VSD_INDIRECT & vsd) {
- uint32_t nr_pages = vst_tsize / XIVE_VSD_SIZE;
- uint32_t page_shift;
-
- vsd = ldq_be_dma(&address_space_memory, vsd & VSD_ADDRESS_MASK);
- page_shift = GETFIELD(VSD_TSIZE, vsd) + 12;
-
- if (!pnv_xive_vst_page_size_allowed(page_shift)) {
- return 0;
- }
-
- return nr_pages * (1ull << page_shift);
- }
-
- return vst_tsize;
-}
-
static uint64_t pnv_xive_vst_addr_direct(PnvXive *xive, uint32_t type,
uint64_t vsd, uint32_t idx)
{
const XiveVstInfo *info = &vst_infos[type];
uint64_t vst_addr = vsd & VSD_ADDRESS_MASK;
+ uint64_t vst_tsize = 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12);
+ uint32_t idx_max;
+
+ idx_max = vst_tsize / info->size - 1;
+ if (idx > idx_max) {
+#ifdef XIVE_DEBUG
+ xive_error(xive, "VST: %s entry %x out of range [ 0 .. %x ] !?",
+ info->name, idx, idx_max);
+#endif
+ return 0;
+ }
return vst_addr + idx * info->size;
}
@@ -171,7 +174,9 @@ static uint64_t pnv_xive_vst_addr_indirect(PnvXive *xive, uint32_t type,
vsd = ldq_be_dma(&address_space_memory, vsd_addr);
if (!(vsd & VSD_ADDRESS_MASK)) {
+#ifdef XIVE_DEBUG
xive_error(xive, "VST: invalid %s entry %x !?", info->name, idx);
+#endif
return 0;
}
@@ -192,7 +197,9 @@ static uint64_t pnv_xive_vst_addr_indirect(PnvXive *xive, uint32_t type,
vsd = ldq_be_dma(&address_space_memory, vsd_addr);
if (!(vsd & VSD_ADDRESS_MASK)) {
+#ifdef XIVE_DEBUG
xive_error(xive, "VST: invalid %s entry %x !?", info->name, idx);
+#endif
return 0;
}
@@ -215,7 +222,6 @@ static uint64_t pnv_xive_vst_addr(PnvXive *xive, uint32_t type, uint8_t blk,
{
const XiveVstInfo *info = &vst_infos[type];
uint64_t vsd;
- uint32_t idx_max;
if (blk >= info->max_blocks) {
xive_error(xive, "VST: invalid block id %d for VST %s %d !?",
@@ -227,20 +233,11 @@ static uint64_t pnv_xive_vst_addr(PnvXive *xive, uint32_t type, uint8_t blk,
/* Remote VST access */
if (GETFIELD(VSD_MODE, vsd) == VSD_MODE_FORWARD) {
- xive = pnv_xive_get_ic(blk);
+ xive = pnv_xive_get_remote(blk);
return xive ? pnv_xive_vst_addr(xive, type, blk, idx) : 0;
}
- idx_max = pnv_xive_vst_size(vsd) / info->size - 1;
- if (idx > idx_max) {
-#ifdef XIVE_DEBUG
- xive_error(xive, "VST: %s entry %x/%x out of range [ 0 .. %x ] !?",
- info->name, blk, idx, idx_max);
-#endif
- return 0;
- }
-
if (VSD_INDIRECT & vsd) {
return pnv_xive_vst_addr_indirect(xive, type, vsd, idx);
}
@@ -384,7 +381,10 @@ static int pnv_xive_get_eas(XiveRouter *xrtr, uint8_t blk, uint32_t idx,
{
PnvXive *xive = PNV_XIVE(xrtr);
- if (pnv_xive_get_ic(blk) != xive) {
+ /*
+ * EAT lookups should be local to the IC
+ */
+ if (pnv_xive_block_id(xive) != blk) {
xive_error(xive, "VST: EAS %x is remote !?", XIVE_EAS(blk, idx));
return -1;
}
@@ -392,31 +392,97 @@ static int pnv_xive_get_eas(XiveRouter *xrtr, uint8_t blk, uint32_t idx,
return pnv_xive_vst_read(xive, VST_TSEL_IVT, blk, idx, eas);
}
-static XiveTCTX *pnv_xive_get_tctx(XiveRouter *xrtr, CPUState *cs)
+/*
+ * One bit per thread id. The first register PC_THREAD_EN_REG0 covers
+ * the first cores 0-15 (normal) of the chip or 0-7 (fused). The
+ * second register covers cores 16-23 (normal) or 8-11 (fused).
+ */
+static bool pnv_xive_is_cpu_enabled(PnvXive *xive, PowerPCCPU *cpu)
{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
- PnvXive *xive = NULL;
- CPUPPCState *env = &cpu->env;
- int pir = env->spr_cb[SPR_PIR].default_value;
+ int pir = ppc_cpu_pir(cpu);
+ uint32_t fc = PNV9_PIR2FUSEDCORE(pir);
+ uint64_t reg = fc < 8 ? PC_THREAD_EN_REG0 : PC_THREAD_EN_REG1;
+ uint32_t bit = pir & 0x3f;
- /*
- * Perform an extra check on the HW thread enablement.
- *
- * The TIMA is shared among the chips and to identify the chip
- * from which the access is being done, we extract the chip id
- * from the PIR.
- */
- xive = pnv_xive_get_ic((pir >> 8) & 0xf);
- if (!xive) {
- return NULL;
- }
+ return xive->regs[reg >> 3] & PPC_BIT(bit);
+}
+
+static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format,
+ uint8_t nvt_blk, uint32_t nvt_idx,
+ bool cam_ignore, uint8_t priority,
+ uint32_t logic_serv, XiveTCTXMatch *match)
+{
+ PnvXive *xive = PNV_XIVE(xptr);
+ PnvChip *chip = xive->chip;
+ int count = 0;
+ int i, j;
+
+ for (i = 0; i < chip->nr_cores; i++) {
+ PnvCore *pc = chip->cores[i];
+ CPUCore *cc = CPU_CORE(pc);
+
+ for (j = 0; j < cc->nr_threads; j++) {
+ PowerPCCPU *cpu = pc->threads[j];
+ XiveTCTX *tctx;
+ int ring;
+
+ if (!pnv_xive_is_cpu_enabled(xive, cpu)) {
+ continue;
+ }
- if (!(xive->regs[PC_THREAD_EN_REG0 >> 3] & PPC_BIT(pir & 0x3f))) {
- xive_error(PNV_XIVE(xrtr), "IC: CPU %x is not enabled", pir);
+ tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
+
+ /*
+ * Check the thread context CAM lines and record matches.
+ */
+ ring = xive_presenter_tctx_match(xptr, tctx, format, nvt_blk,
+ nvt_idx, cam_ignore, logic_serv);
+ /*
+ * Save the context and follow on to catch duplicates, that we
+ * don't support yet.
+ */
+ if (ring != -1) {
+ if (match->tctx) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a "
+ "thread context NVT %x/%x\n",
+ nvt_blk, nvt_idx);
+ return -1;
+ }
+
+ match->ring = ring;
+ match->tctx = tctx;
+ count++;
+ }
+ }
}
- return tctx;
+ return count;
+}
+
+static uint8_t pnv_xive_get_block_id(XiveRouter *xrtr)
+{
+ return pnv_xive_block_id(PNV_XIVE(xrtr));
+}
+
+/*
+ * The TIMA MMIO space is shared among the chips and to identify the
+ * chip from which the access is being done, we extract the chip id
+ * from the PIR.
+ */
+static PnvXive *pnv_xive_tm_get_xive(PowerPCCPU *cpu)
+{
+ int pir = ppc_cpu_pir(cpu);
+ PnvChip *chip;
+ PnvXive *xive;
+
+ chip = pnv_get_chip(PNV9_PIR2CHIP(pir));
+ assert(chip);
+ xive = &PNV9_CHIP(chip)->xive;
+
+ if (!pnv_xive_is_cpu_enabled(xive, cpu)) {
+ xive_error(xive, "IC: CPU %x is not enabled", pir);
+ }
+ return xive;
}
/*
@@ -429,7 +495,7 @@ static XiveTCTX *pnv_xive_get_tctx(XiveRouter *xrtr, CPUState *cs)
static void pnv_xive_notify(XiveNotifier *xn, uint32_t srcno)
{
PnvXive *xive = PNV_XIVE(xn);
- uint8_t blk = xive->chip->chip_id;
+ uint8_t blk = pnv_xive_block_id(xive);
xive_router_notify(xn, XIVE_EAS(blk, srcno));
}
@@ -453,19 +519,50 @@ static uint64_t pnv_xive_pc_size(PnvXive *xive)
return (~xive->regs[CQ_PC_BARM >> 3] + 1) & CQ_PC_BARM_MASK;
}
-static uint32_t pnv_xive_nr_ipis(PnvXive *xive)
+static uint32_t pnv_xive_nr_ipis(PnvXive *xive, uint8_t blk)
{
- uint8_t blk = xive->chip->chip_id;
+ uint64_t vsd = xive->vsds[VST_TSEL_SBE][blk];
+ uint64_t vst_tsize = 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12);
- return pnv_xive_vst_size(xive->vsds[VST_TSEL_SBE][blk]) * SBE_PER_BYTE;
+ return VSD_INDIRECT & vsd ? 0 : vst_tsize * SBE_PER_BYTE;
}
-static uint32_t pnv_xive_nr_ends(PnvXive *xive)
+/*
+ * Compute the number of entries per indirect subpage.
+ */
+static uint64_t pnv_xive_vst_per_subpage(PnvXive *xive, uint32_t type)
{
- uint8_t blk = xive->chip->chip_id;
+ uint8_t blk = pnv_xive_block_id(xive);
+ uint64_t vsd = xive->vsds[type][blk];
+ const XiveVstInfo *info = &vst_infos[type];
+ uint64_t vsd_addr;
+ uint32_t page_shift;
+
+ /* For direct tables, fake a valid value */
+ if (!(VSD_INDIRECT & vsd)) {
+ return 1;
+ }
+
+ /* Get the page size of the indirect table. */
+ vsd_addr = vsd & VSD_ADDRESS_MASK;
+ vsd = ldq_be_dma(&address_space_memory, vsd_addr);
- return pnv_xive_vst_size(xive->vsds[VST_TSEL_EQDT][blk])
- / vst_infos[VST_TSEL_EQDT].size;
+ if (!(vsd & VSD_ADDRESS_MASK)) {
+#ifdef XIVE_DEBUG
+ xive_error(xive, "VST: invalid %s entry %x !?", info->name, idx);
+#endif
+ return 0;
+ }
+
+ page_shift = GETFIELD(VSD_TSIZE, vsd) + 12;
+
+ if (!pnv_xive_vst_page_size_allowed(page_shift)) {
+ xive_error(xive, "VST: invalid %s page shift %d", info->name,
+ page_shift);
+ return 0;
+ }
+
+ return (1ull << page_shift) / info->size;
}
/*
@@ -598,6 +695,7 @@ static void pnv_xive_vst_set_exclusive(PnvXive *xive, uint8_t type,
XiveSource *xsrc = &xive->ipi_source;
const XiveVstInfo *info = &vst_infos[type];
uint32_t page_shift = GETFIELD(VSD_TSIZE, vsd) + 12;
+ uint64_t vst_tsize = 1ull << page_shift;
uint64_t vst_addr = vsd & VSD_ADDRESS_MASK;
/* Basic checks */
@@ -633,11 +731,16 @@ static void pnv_xive_vst_set_exclusive(PnvXive *xive, uint8_t type,
case VST_TSEL_EQDT:
/*
- * Backing store pages for the END. Compute the number of ENDs
- * provisioned by FW and resize the END ESB window accordingly.
+ * Backing store pages for the END.
+ *
+ * If the table is direct, we can compute the number of PQ
+ * entries provisioned by FW (such as skiboot) and resize the
+ * END ESB window accordingly.
*/
- memory_region_set_size(&end_xsrc->esb_mmio, pnv_xive_nr_ends(xive) *
- (1ull << (end_xsrc->esb_shift + 1)));
+ if (!(VSD_INDIRECT & vsd)) {
+ memory_region_set_size(&end_xsrc->esb_mmio, (vst_tsize / info->size)
+ * (1ull << xsrc->esb_shift));
+ }
memory_region_add_subregion(&xive->end_edt_mmio, 0,
&end_xsrc->esb_mmio);
break;
@@ -646,11 +749,16 @@ static void pnv_xive_vst_set_exclusive(PnvXive *xive, uint8_t type,
/*
* Backing store pages for the source PQ bits. The model does
* not use these PQ bits backed in RAM because the XiveSource
- * model has its own. Compute the number of IRQs provisioned
- * by FW and resize the IPI ESB window accordingly.
+ * model has its own.
+ *
+ * If the table is direct, we can compute the number of PQ
+ * entries provisioned by FW (such as skiboot) and resize the
+ * ESB window accordingly.
*/
- memory_region_set_size(&xsrc->esb_mmio, pnv_xive_nr_ipis(xive) *
- (1ull << xsrc->esb_shift));
+ if (!(VSD_INDIRECT & vsd)) {
+ memory_region_set_size(&xsrc->esb_mmio, vst_tsize * SBE_PER_BYTE
+ * (1ull << xsrc->esb_shift));
+ }
memory_region_add_subregion(&xive->ipi_edt_mmio, 0, &xsrc->esb_mmio);
break;
@@ -789,20 +897,7 @@ static void pnv_xive_ic_reg_write(void *opaque, hwaddr offset,
case PC_TCTXT_CFG:
/*
* TODO: block group support
- *
- * PC_TCTXT_CFG_BLKGRP_EN
- * PC_TCTXT_CFG_HARD_CHIPID_BLK :
- * Moves the chipid into block field for hardwired CAM compares.
- * Block offset value is adjusted to 0b0..01 & ThrdId
- *
- * Will require changes in xive_presenter_tctx_match(). I am
- * not sure how to handle that yet.
*/
-
- /* Overrides hardwired chip ID with the chip ID field */
- if (val & PC_TCTXT_CHIPID_OVERRIDE) {
- xive->tctx_chipid = GETFIELD(PC_TCTXT_CHIPID, val);
- }
break;
case PC_TCTXT_TRACK:
/*
@@ -1349,12 +1444,13 @@ static const MemoryRegionOps pnv_xive_ic_lsi_ops = {
*/
/*
- * When the TIMA is accessed from the indirect page, the thread id
- * (PIR) has to be configured in the IC registers before. This is used
- * for resets and for debug purpose also.
+ * When the TIMA is accessed from the indirect page, the thread id of
+ * the target CPU is configured in the PC_TCTXT_INDIR0 register before
+ * use. This is used for resets and for debug purpose also.
*/
static XiveTCTX *pnv_xive_get_indirect_tctx(PnvXive *xive)
{
+ PnvChip *chip = xive->chip;
uint64_t tctxt_indir = xive->regs[PC_TCTXT_INDIR0 >> 3];
PowerPCCPU *cpu = NULL;
int pir;
@@ -1364,15 +1460,15 @@ static XiveTCTX *pnv_xive_get_indirect_tctx(PnvXive *xive)
return NULL;
}
- pir = GETFIELD(PC_TCTXT_INDIR_THRDID, tctxt_indir) & 0xff;
- cpu = ppc_get_vcpu_by_pir(pir);
+ pir = (chip->chip_id << 8) | GETFIELD(PC_TCTXT_INDIR_THRDID, tctxt_indir);
+ cpu = pnv_chip_find_cpu(chip, pir);
if (!cpu) {
xive_error(xive, "IC: invalid PIR %x for indirect access", pir);
return NULL;
}
/* Check that HW thread is XIVE enabled */
- if (!(xive->regs[PC_THREAD_EN_REG0 >> 3] & PPC_BIT(pir & 0x3f))) {
+ if (!pnv_xive_is_cpu_enabled(xive, cpu)) {
xive_error(xive, "IC: CPU %x is not enabled", pir);
}
@@ -1384,7 +1480,7 @@ static void xive_tm_indirect_write(void *opaque, hwaddr offset,
{
XiveTCTX *tctx = pnv_xive_get_indirect_tctx(PNV_XIVE(opaque));
- xive_tctx_tm_write(tctx, offset, value, size);
+ xive_tctx_tm_write(XIVE_PRESENTER(opaque), tctx, offset, value, size);
}
static uint64_t xive_tm_indirect_read(void *opaque, hwaddr offset,
@@ -1392,7 +1488,7 @@ static uint64_t xive_tm_indirect_read(void *opaque, hwaddr offset,
{
XiveTCTX *tctx = pnv_xive_get_indirect_tctx(PNV_XIVE(opaque));
- return xive_tctx_tm_read(tctx, offset, size);
+ return xive_tctx_tm_read(XIVE_PRESENTER(opaque), tctx, offset, size);
}
static const MemoryRegionOps xive_tm_indirect_ops = {
@@ -1409,6 +1505,39 @@ static const MemoryRegionOps xive_tm_indirect_ops = {
},
};
+static void pnv_xive_tm_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(current_cpu);
+ PnvXive *xive = pnv_xive_tm_get_xive(cpu);
+ XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
+
+ xive_tctx_tm_write(XIVE_PRESENTER(xive), tctx, offset, value, size);
+}
+
+static uint64_t pnv_xive_tm_read(void *opaque, hwaddr offset, unsigned size)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(current_cpu);
+ PnvXive *xive = pnv_xive_tm_get_xive(cpu);
+ XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
+
+ return xive_tctx_tm_read(XIVE_PRESENTER(xive), tctx, offset, size);
+}
+
+const MemoryRegionOps pnv_xive_tm_ops = {
+ .read = pnv_xive_tm_read,
+ .write = pnv_xive_tm_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 8,
+ },
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 8,
+ },
+};
+
/*
* Interrupt controller XSCOM region.
*/
@@ -1574,23 +1703,40 @@ static const MemoryRegionOps pnv_xive_pc_ops = {
},
};
+static void xive_nvt_pic_print_info(XiveNVT *nvt, uint32_t nvt_idx,
+ Monitor *mon)
+{
+ uint8_t eq_blk = xive_get_field32(NVT_W1_EQ_BLOCK, nvt->w1);
+ uint32_t eq_idx = xive_get_field32(NVT_W1_EQ_INDEX, nvt->w1);
+
+ if (!xive_nvt_is_valid(nvt)) {
+ return;
+ }
+
+ monitor_printf(mon, " %08x end:%02x/%04x IPB:%02x\n", nvt_idx,
+ eq_blk, eq_idx,
+ xive_get_field32(NVT_W4_IPB, nvt->w4));
+}
+
void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon)
{
XiveRouter *xrtr = XIVE_ROUTER(xive);
- uint8_t blk = xive->chip->chip_id;
+ uint8_t blk = pnv_xive_block_id(xive);
+ uint8_t chip_id = xive->chip->chip_id;
uint32_t srcno0 = XIVE_EAS(blk, 0);
- uint32_t nr_ipis = pnv_xive_nr_ipis(xive);
- uint32_t nr_ends = pnv_xive_nr_ends(xive);
+ uint32_t nr_ipis = pnv_xive_nr_ipis(xive, blk);
XiveEAS eas;
XiveEND end;
+ XiveNVT nvt;
int i;
+ uint64_t xive_nvt_per_subpage;
- monitor_printf(mon, "XIVE[%x] Source %08x .. %08x\n", blk, srcno0,
- srcno0 + nr_ipis - 1);
+ monitor_printf(mon, "XIVE[%x] #%d Source %08x .. %08x\n", chip_id, blk,
+ srcno0, srcno0 + nr_ipis - 1);
xive_source_pic_print_info(&xive->ipi_source, srcno0, mon);
- monitor_printf(mon, "XIVE[%x] EAT %08x .. %08x\n", blk, srcno0,
- srcno0 + nr_ipis - 1);
+ monitor_printf(mon, "XIVE[%x] #%d EAT %08x .. %08x\n", chip_id, blk,
+ srcno0, srcno0 + nr_ipis - 1);
for (i = 0; i < nr_ipis; i++) {
if (xive_router_get_eas(xrtr, blk, i, &eas)) {
break;
@@ -1600,21 +1746,25 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon)
}
}
- monitor_printf(mon, "XIVE[%x] ENDT %08x .. %08x\n", blk, 0, nr_ends - 1);
- for (i = 0; i < nr_ends; i++) {
- if (xive_router_get_end(xrtr, blk, i, &end)) {
- break;
- }
- xive_end_pic_print_info(&end, i, mon);
+ monitor_printf(mon, "XIVE[%x] #%d ENDT\n", chip_id, blk);
+ i = 0;
+ while (!xive_router_get_end(xrtr, blk, i, &end)) {
+ xive_end_pic_print_info(&end, i++, mon);
}
- monitor_printf(mon, "XIVE[%x] END Escalation %08x .. %08x\n", blk, 0,
- nr_ends - 1);
- for (i = 0; i < nr_ends; i++) {
- if (xive_router_get_end(xrtr, blk, i, &end)) {
- break;
+ monitor_printf(mon, "XIVE[%x] #%d END Escalation EAT\n", chip_id, blk);
+ i = 0;
+ while (!xive_router_get_end(xrtr, blk, i, &end)) {
+ xive_end_eas_pic_print_info(&end, i++, mon);
+ }
+
+ monitor_printf(mon, "XIVE[%x] #%d NVTT %08x .. %08x\n", chip_id, blk,
+ 0, XIVE_NVT_COUNT - 1);
+ xive_nvt_per_subpage = pnv_xive_vst_per_subpage(xive, VST_TSEL_VPDT);
+ for (i = 0; i < XIVE_NVT_COUNT; i += xive_nvt_per_subpage) {
+ while (!xive_router_get_nvt(xrtr, blk, i, &nvt)) {
+ xive_nvt_pic_print_info(&nvt, i++, mon);
}
- xive_end_eas_pic_print_info(&end, i, mon);
}
}
@@ -1624,12 +1774,6 @@ static void pnv_xive_reset(void *dev)
XiveSource *xsrc = &xive->ipi_source;
XiveENDSource *end_xsrc = &xive->end_source;
- /*
- * Use the PnvChip id to identify the XIVE interrupt controller.
- * It can be overriden by configuration at runtime.
- */
- xive->tctx_chipid = xive->chip->chip_id;
-
/* Default page size (Should be changed at runtime to 64k) */
xive->ic_shift = xive->vc_shift = xive->pc_shift = 12;
@@ -1675,17 +1819,8 @@ static void pnv_xive_realize(DeviceState *dev, Error **errp)
XiveSource *xsrc = &xive->ipi_source;
XiveENDSource *end_xsrc = &xive->end_source;
Error *local_err = NULL;
- Object *obj;
- obj = object_property_get_link(OBJECT(dev), "chip", &local_err);
- if (!obj) {
- error_propagate(errp, local_err);
- error_prepend(errp, "required link 'chip' not found: ");
- return;
- }
-
- /* The PnvChip id identifies the XIVE interrupt controller. */
- xive->chip = PNV_CHIP(obj);
+ assert(xive->chip);
/*
* The XiveSource and XiveENDSource objects are realized with the
@@ -1695,8 +1830,8 @@ static void pnv_xive_realize(DeviceState *dev, Error **errp)
*/
object_property_set_int(OBJECT(xsrc), PNV_XIVE_NR_IRQS, "nr-irqs",
&error_fatal);
- object_property_add_const_link(OBJECT(xsrc), "xive", OBJECT(xive),
- &error_fatal);
+ object_property_set_link(OBJECT(xsrc), OBJECT(xive), "xive",
+ &error_abort);
object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err);
if (local_err) {
error_propagate(errp, local_err);
@@ -1705,8 +1840,8 @@ static void pnv_xive_realize(DeviceState *dev, Error **errp)
object_property_set_int(OBJECT(end_xsrc), PNV_XIVE_NR_ENDS, "nr-ends",
&error_fatal);
- object_property_add_const_link(OBJECT(end_xsrc), "xive", OBJECT(xive),
- &error_fatal);
+ object_property_set_link(OBJECT(end_xsrc), OBJECT(xive), "xive",
+ &error_abort);
object_property_set_bool(OBJECT(end_xsrc), true, "realized", &local_err);
if (local_err) {
error_propagate(errp, local_err);
@@ -1766,7 +1901,7 @@ static void pnv_xive_realize(DeviceState *dev, Error **errp)
"xive-pc", PNV9_XIVE_PC_SIZE);
/* Thread Interrupt Management Area (Direct) */
- memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &xive_tm_ops,
+ memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &pnv_xive_tm_ops,
xive, "xive-tima", PNV9_XIVE_TM_SIZE);
qemu_register_reset(pnv_xive_reset, dev);
@@ -1800,6 +1935,8 @@ static Property pnv_xive_properties[] = {
DEFINE_PROP_UINT64("vc-bar", PnvXive, vc_base, 0),
DEFINE_PROP_UINT64("pc-bar", PnvXive, pc_base, 0),
DEFINE_PROP_UINT64("tm-bar", PnvXive, tm_base, 0),
+ /* The PnvChip id identifies the XIVE interrupt controller. */
+ DEFINE_PROP_LINK("chip", PnvXive, chip, TYPE_PNV_CHIP, PnvChip *),
DEFINE_PROP_END_OF_LIST(),
};
@@ -1809,6 +1946,7 @@ static void pnv_xive_class_init(ObjectClass *klass, void *data)
PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);
XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass);
XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass);
+ XivePresenterClass *xpc = XIVE_PRESENTER_CLASS(klass);
xdc->dt_xscom = pnv_xive_dt_xscom;
@@ -1821,9 +1959,10 @@ static void pnv_xive_class_init(ObjectClass *klass, void *data)
xrc->write_end = pnv_xive_write_end;
xrc->get_nvt = pnv_xive_get_nvt;
xrc->write_nvt = pnv_xive_write_nvt;
- xrc->get_tctx = pnv_xive_get_tctx;
+ xrc->get_block_id = pnv_xive_get_block_id;
xnc->notify = pnv_xive_notify;
+ xpc->match_nvt = pnv_xive_match_nvt;
};
static const TypeInfo pnv_xive_info = {
diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
index 9cb8d38..57305c5 100644
--- a/hw/intc/spapr_xive.c
+++ b/hw/intc/spapr_xive.c
@@ -205,6 +205,35 @@ void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable)
memory_region_set_enabled(&xive->end_source.esb_mmio, false);
}
+static void spapr_xive_tm_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+ XiveTCTX *tctx = spapr_cpu_state(POWERPC_CPU(current_cpu))->tctx;
+
+ xive_tctx_tm_write(XIVE_PRESENTER(opaque), tctx, offset, value, size);
+}
+
+static uint64_t spapr_xive_tm_read(void *opaque, hwaddr offset, unsigned size)
+{
+ XiveTCTX *tctx = spapr_cpu_state(POWERPC_CPU(current_cpu))->tctx;
+
+ return xive_tctx_tm_read(XIVE_PRESENTER(opaque), tctx, offset, size);
+}
+
+const MemoryRegionOps spapr_xive_tm_ops = {
+ .read = spapr_xive_tm_read,
+ .write = spapr_xive_tm_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 8,
+ },
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 8,
+ },
+};
+
static void spapr_xive_end_reset(XiveEND *end)
{
memset(end, 0, sizeof(*end));
@@ -276,8 +305,8 @@ static void spapr_xive_realize(DeviceState *dev, Error **errp)
*/
object_property_set_int(OBJECT(xsrc), xive->nr_irqs, "nr-irqs",
&error_fatal);
- object_property_add_const_link(OBJECT(xsrc), "xive", OBJECT(xive),
- &error_fatal);
+ object_property_set_link(OBJECT(xsrc), OBJECT(xive), "xive",
+ &error_abort);
object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err);
if (local_err) {
error_propagate(errp, local_err);
@@ -290,8 +319,8 @@ static void spapr_xive_realize(DeviceState *dev, Error **errp)
*/
object_property_set_int(OBJECT(end_xsrc), xive->nr_irqs, "nr-ends",
&error_fatal);
- object_property_add_const_link(OBJECT(end_xsrc), "xive", OBJECT(xive),
- &error_fatal);
+ object_property_set_link(OBJECT(end_xsrc), OBJECT(xive), "xive",
+ &error_abort);
object_property_set_bool(OBJECT(end_xsrc), true, "realized", &local_err);
if (local_err) {
error_propagate(errp, local_err);
@@ -314,8 +343,8 @@ static void spapr_xive_realize(DeviceState *dev, Error **errp)
qemu_register_reset(spapr_xive_reset, dev);
/* TIMA initialization */
- memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &xive_tm_ops, xive,
- "xive.tima", 4ull << TM_SHIFT);
+ memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &spapr_xive_tm_ops,
+ xive, "xive.tima", 4ull << TM_SHIFT);
sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xive->tm_mmio);
/*
@@ -398,11 +427,55 @@ static int spapr_xive_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk,
g_assert_not_reached();
}
-static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs)
+static int spapr_xive_match_nvt(XivePresenter *xptr, uint8_t format,
+ uint8_t nvt_blk, uint32_t nvt_idx,
+ bool cam_ignore, uint8_t priority,
+ uint32_t logic_serv, XiveTCTXMatch *match)
{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
+ CPUState *cs;
+ int count = 0;
+
+ CPU_FOREACH(cs) {
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ XiveTCTX *tctx = spapr_cpu_state(cpu)->tctx;
+ int ring;
+
+ /*
+ * Skip partially initialized vCPUs. This can happen when
+ * vCPUs are hotplugged.
+ */
+ if (!tctx) {
+ continue;
+ }
- return spapr_cpu_state(cpu)->tctx;
+ /*
+ * Check the thread context CAM lines and record matches.
+ */
+ ring = xive_presenter_tctx_match(xptr, tctx, format, nvt_blk, nvt_idx,
+ cam_ignore, logic_serv);
+ /*
+ * Save the matching thread interrupt context and follow on to
+ * check for duplicates which are invalid.
+ */
+ if (ring != -1) {
+ if (match->tctx) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a thread "
+ "context NVT %x/%x\n", nvt_blk, nvt_idx);
+ return -1;
+ }
+
+ match->ring = ring;
+ match->tctx = tctx;
+ count++;
+ }
+ }
+
+ return count;
+}
+
+static uint8_t spapr_xive_get_block_id(XiveRouter *xrtr)
+{
+ return SPAPR_XIVE_BLOCK_ID;
}
static const VMStateDescription vmstate_spapr_xive_end = {
@@ -651,12 +724,14 @@ static void spapr_xive_dt(SpaprInterruptController *intc, uint32_t nr_servers,
plat_res_int_priorities, sizeof(plat_res_int_priorities)));
}
-static int spapr_xive_activate(SpaprInterruptController *intc, Error **errp)
+static int spapr_xive_activate(SpaprInterruptController *intc,
+ uint32_t nr_servers, Error **errp)
{
SpaprXive *xive = SPAPR_XIVE(intc);
if (kvm_enabled()) {
- int rc = spapr_irq_init_kvm(kvmppc_xive_connect, intc, errp);
+ int rc = spapr_irq_init_kvm(kvmppc_xive_connect, intc, nr_servers,
+ errp);
if (rc < 0) {
return rc;
}
@@ -684,6 +759,7 @@ static void spapr_xive_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass);
SpaprInterruptControllerClass *sicc = SPAPR_INTC_CLASS(klass);
+ XivePresenterClass *xpc = XIVE_PRESENTER_CLASS(klass);
dc->desc = "sPAPR XIVE Interrupt Controller";
dc->props = spapr_xive_properties;
@@ -695,7 +771,7 @@ static void spapr_xive_class_init(ObjectClass *klass, void *data)
xrc->write_end = spapr_xive_write_end;
xrc->get_nvt = spapr_xive_get_nvt;
xrc->write_nvt = spapr_xive_write_nvt;
- xrc->get_tctx = spapr_xive_get_tctx;
+ xrc->get_block_id = spapr_xive_get_block_id;
sicc->activate = spapr_xive_activate;
sicc->deactivate = spapr_xive_deactivate;
@@ -708,6 +784,8 @@ static void spapr_xive_class_init(ObjectClass *klass, void *data)
sicc->print_info = spapr_xive_print_info;
sicc->dt = spapr_xive_dt;
sicc->post_load = spapr_xive_post_load;
+
+ xpc->match_nvt = spapr_xive_match_nvt;
}
static const TypeInfo spapr_xive_info = {
diff --git a/hw/intc/spapr_xive_kvm.c b/hw/intc/spapr_xive_kvm.c
index 08012ac..32b2809 100644
--- a/hw/intc/spapr_xive_kvm.c
+++ b/hw/intc/spapr_xive_kvm.c
@@ -152,7 +152,8 @@ void kvmppc_xive_cpu_synchronize_state(XiveTCTX *tctx, Error **errp)
void kvmppc_xive_cpu_connect(XiveTCTX *tctx, Error **errp)
{
- SpaprXive *xive = SPAPR_MACHINE(qdev_get_machine())->xive;
+ MachineState *ms = MACHINE(qdev_get_machine());
+ SpaprXive *xive = SPAPR_MACHINE(ms)->xive;
unsigned long vcpu_id;
int ret;
@@ -171,8 +172,16 @@ void kvmppc_xive_cpu_connect(XiveTCTX *tctx, Error **errp)
ret = kvm_vcpu_enable_cap(tctx->cs, KVM_CAP_PPC_IRQ_XIVE, 0, xive->fd,
vcpu_id, 0);
if (ret < 0) {
- error_setg(errp, "XIVE: unable to connect CPU%ld to KVM device: %s",
+ Error *local_err = NULL;
+
+ error_setg(&local_err,
+ "XIVE: unable to connect CPU%ld to KVM device: %s",
vcpu_id, strerror(errno));
+ if (errno == ENOSPC) {
+ error_append_hint(&local_err, "Try -smp maxcpus=N with N < %u\n",
+ ms->smp.max_cpus);
+ }
+ error_propagate(errp, local_err);
return;
}
@@ -354,32 +363,20 @@ static void kvmppc_xive_source_get_state(XiveSource *xsrc)
void kvmppc_xive_source_set_irq(void *opaque, int srcno, int val)
{
XiveSource *xsrc = opaque;
- SpaprXive *xive = SPAPR_XIVE(xsrc->xive);
- struct kvm_irq_level args;
- int rc;
- /* The KVM XIVE device should be in use */
- assert(xive->fd != -1);
-
- args.irq = srcno;
if (!xive_source_irq_is_lsi(xsrc, srcno)) {
if (!val) {
return;
}
- args.level = KVM_INTERRUPT_SET;
} else {
if (val) {
xsrc->status[srcno] |= XIVE_STATUS_ASSERTED;
- args.level = KVM_INTERRUPT_SET_LEVEL;
} else {
xsrc->status[srcno] &= ~XIVE_STATUS_ASSERTED;
- args.level = KVM_INTERRUPT_UNSET;
}
}
- rc = kvm_vm_ioctl(kvm_state, KVM_IRQ_LINE, &args);
- if (rc < 0) {
- error_report("XIVE: kvm_irq_line() failed : %s", strerror(errno));
- }
+
+ xive_esb_trigger(xsrc, srcno);
}
/*
@@ -740,7 +737,8 @@ static void *kvmppc_xive_mmap(SpaprXive *xive, int pgoff, size_t len,
* All the XIVE memory regions are now backed by mappings from the KVM
* XIVE device.
*/
-int kvmppc_xive_connect(SpaprInterruptController *intc, Error **errp)
+int kvmppc_xive_connect(SpaprInterruptController *intc, uint32_t nr_servers,
+ Error **errp)
{
SpaprXive *xive = SPAPR_XIVE(intc);
XiveSource *xsrc = &xive->source;
@@ -769,6 +767,16 @@ int kvmppc_xive_connect(SpaprInterruptController *intc, Error **errp)
return -1;
}
+ /* Tell KVM about the # of VCPUs we may have */
+ if (kvm_device_check_attr(xive->fd, KVM_DEV_XIVE_GRP_CTRL,
+ KVM_DEV_XIVE_NR_SERVERS)) {
+ if (kvm_device_access(xive->fd, KVM_DEV_XIVE_GRP_CTRL,
+ KVM_DEV_XIVE_NR_SERVERS, &nr_servers, true,
+ &local_err)) {
+ goto fail;
+ }
+ }
+
/*
* 1. Source ESB pages - KVM mapping
*/
diff --git a/hw/intc/xics.c b/hw/intc/xics.c
index e7ac9ba..1952009 100644
--- a/hw/intc/xics.c
+++ b/hw/intc/xics.c
@@ -289,9 +289,6 @@ void icp_reset(ICPState *icp)
icp->pending_priority = 0xff;
icp->mfrr = 0xff;
- /* Make all outputs are deasserted */
- qemu_set_irq(icp->output, 0);
-
if (kvm_irqchip_in_kernel()) {
Error *local_err = NULL;
@@ -305,33 +302,13 @@ void icp_reset(ICPState *icp)
static void icp_realize(DeviceState *dev, Error **errp)
{
ICPState *icp = ICP(dev);
- PowerPCCPU *cpu;
CPUPPCState *env;
- Object *obj;
Error *err = NULL;
- obj = object_property_get_link(OBJECT(dev), ICP_PROP_XICS, &err);
- if (!obj) {
- error_propagate_prepend(errp, err,
- "required link '" ICP_PROP_XICS
- "' not found: ");
- return;
- }
-
- icp->xics = XICS_FABRIC(obj);
-
- obj = object_property_get_link(OBJECT(dev), ICP_PROP_CPU, &err);
- if (!obj) {
- error_propagate_prepend(errp, err,
- "required link '" ICP_PROP_CPU
- "' not found: ");
- return;
- }
-
- cpu = POWERPC_CPU(obj);
- icp->cs = CPU(obj);
+ assert(icp->xics);
+ assert(icp->cs);
- env = &cpu->env;
+ env = &POWERPC_CPU(icp->cs)->env;
switch (PPC_INPUT(env)) {
case PPC_FLAGS_INPUT_POWER7:
icp->output = env->irq_inputs[POWER7_INPUT_INT];
@@ -368,12 +345,20 @@ static void icp_unrealize(DeviceState *dev, Error **errp)
vmstate_unregister(NULL, &vmstate_icp_server, icp);
}
+static Property icp_properties[] = {
+ DEFINE_PROP_LINK(ICP_PROP_XICS, ICPState, xics, TYPE_XICS_FABRIC,
+ XICSFabric *),
+ DEFINE_PROP_LINK(ICP_PROP_CPU, ICPState, cs, TYPE_CPU, CPUState *),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void icp_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = icp_realize;
dc->unrealize = icp_unrealize;
+ dc->props = icp_properties;
/*
* Reason: part of XICS interrupt controller, needs to be wired up
* by icp_create().
@@ -397,11 +382,8 @@ Object *icp_create(Object *cpu, const char *type, XICSFabric *xi, Error **errp)
obj = object_new(type);
object_property_add_child(cpu, type, obj, &error_abort);
object_unref(obj);
- object_ref(OBJECT(xi));
- object_property_add_const_link(obj, ICP_PROP_XICS, OBJECT(xi),
- &error_abort);
- object_ref(cpu);
- object_property_add_const_link(obj, ICP_PROP_CPU, cpu, &error_abort);
+ object_property_set_link(obj, OBJECT(xi), ICP_PROP_XICS, &error_abort);
+ object_property_set_link(obj, cpu, ICP_PROP_CPU, &error_abort);
object_property_set_bool(obj, true, "realized", &local_err);
if (local_err) {
object_unparent(obj);
@@ -416,8 +398,6 @@ void icp_destroy(ICPState *icp)
{
Object *obj = OBJECT(icp);
- object_unref(object_property_get_link(obj, ICP_PROP_CPU, &error_abort));
- object_unref(object_property_get_link(obj, ICP_PROP_XICS, &error_abort));
object_unparent(obj);
}
@@ -609,17 +589,8 @@ static void ics_reset_handler(void *dev)
static void ics_realize(DeviceState *dev, Error **errp)
{
ICSState *ics = ICS(dev);
- Error *local_err = NULL;
- Object *obj;
- obj = object_property_get_link(OBJECT(dev), ICS_PROP_XICS, &local_err);
- if (!obj) {
- error_propagate_prepend(errp, local_err,
- "required link '" ICS_PROP_XICS
- "' not found: ");
- return;
- }
- ics->xics = XICS_FABRIC(obj);
+ assert(ics->xics);
if (!ics->nr_irqs) {
error_setg(errp, "Number of interrupts needs to be greater 0");
@@ -699,6 +670,8 @@ static const VMStateDescription vmstate_ics = {
static Property ics_properties[] = {
DEFINE_PROP_UINT32("nr-irqs", ICSState, nr_irqs, 0),
+ DEFINE_PROP_LINK(ICS_PROP_XICS, ICSState, xics, TYPE_XICS_FABRIC,
+ XICSFabric *),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/hw/intc/xics_kvm.c b/hw/intc/xics_kvm.c
index 954c424..8d61565 100644
--- a/hw/intc/xics_kvm.c
+++ b/hw/intc/xics_kvm.c
@@ -165,8 +165,15 @@ void icp_kvm_realize(DeviceState *dev, Error **errp)
ret = kvm_vcpu_enable_cap(cs, KVM_CAP_IRQ_XICS, 0, kernel_xics_fd, vcpu_id);
if (ret < 0) {
- error_setg(errp, "Unable to connect CPU%ld to kernel XICS: %s", vcpu_id,
- strerror(errno));
+ Error *local_err = NULL;
+
+ error_setg(&local_err, "Unable to connect CPU%ld to kernel XICS: %s",
+ vcpu_id, strerror(errno));
+ if (errno == ENOSPC) {
+ error_append_hint(&local_err, "Try -smp maxcpus=N with N < %u\n",
+ MACHINE(qdev_get_machine())->smp.max_cpus);
+ }
+ error_propagate(errp, local_err);
return;
}
enabled_icp = g_malloc(sizeof(*enabled_icp));
@@ -342,7 +349,8 @@ void ics_kvm_set_irq(ICSState *ics, int srcno, int val)
}
}
-int xics_kvm_connect(SpaprInterruptController *intc, Error **errp)
+int xics_kvm_connect(SpaprInterruptController *intc, uint32_t nr_servers,
+ Error **errp)
{
ICSState *ics = ICS_SPAPR(intc);
int rc;
@@ -398,6 +406,16 @@ int xics_kvm_connect(SpaprInterruptController *intc, Error **errp)
goto fail;
}
+ /* Tell KVM about the # of VCPUs we may have (POWER9 and newer only) */
+ if (kvm_device_check_attr(rc, KVM_DEV_XICS_GRP_CTRL,
+ KVM_DEV_XICS_NR_SERVERS)) {
+ if (kvm_device_access(rc, KVM_DEV_XICS_GRP_CTRL,
+ KVM_DEV_XICS_NR_SERVERS, &nr_servers, true,
+ &local_err)) {
+ goto fail;
+ }
+ }
+
kernel_xics_fd = rc;
kvm_kernel_irqchip = true;
kvm_msi_via_irqfd_allowed = true;
diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c
index b3705da..8ae4f41 100644
--- a/hw/intc/xics_spapr.c
+++ b/hw/intc/xics_spapr.c
@@ -422,10 +422,11 @@ static int xics_spapr_post_load(SpaprInterruptController *intc, int version_id)
return 0;
}
-static int xics_spapr_activate(SpaprInterruptController *intc, Error **errp)
+static int xics_spapr_activate(SpaprInterruptController *intc,
+ uint32_t nr_servers, Error **errp)
{
if (kvm_enabled()) {
- return spapr_irq_init_kvm(xics_kvm_connect, intc, errp);
+ return spapr_irq_init_kvm(xics_kvm_connect, intc, nr_servers, errp);
}
return 0;
}
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 75dce82..d4c6e21 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -47,12 +47,6 @@ static uint8_t ipb_to_pipr(uint8_t ibp)
return ibp ? clz32((uint32_t)ibp << 24) : 0xff;
}
-static void ipb_update(uint8_t *regs, uint8_t priority)
-{
- regs[TM_IPB] |= priority_to_ipb(priority);
- regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]);
-}
-
static uint8_t exception_mask(uint8_t ring)
{
switch (ring) {
@@ -135,6 +129,15 @@ static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr)
xive_tctx_notify(tctx, ring);
}
+void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb)
+{
+ uint8_t *regs = &tctx->regs[ring];
+
+ regs[TM_IPB] |= ipb;
+ regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]);
+ xive_tctx_notify(tctx, ring);
+}
+
static inline uint32_t xive_tctx_word2(uint8_t *ring)
{
return *((uint32_t *) &ring[TM_WORD2]);
@@ -144,19 +147,20 @@ static inline uint32_t xive_tctx_word2(uint8_t *ring)
* XIVE Thread Interrupt Management Area (TIMA)
*/
-static void xive_tm_set_hv_cppr(XiveTCTX *tctx, hwaddr offset,
- uint64_t value, unsigned size)
+static void xive_tm_set_hv_cppr(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, uint64_t value, unsigned size)
{
xive_tctx_set_cppr(tctx, TM_QW3_HV_PHYS, value & 0xff);
}
-static uint64_t xive_tm_ack_hv_reg(XiveTCTX *tctx, hwaddr offset, unsigned size)
+static uint64_t xive_tm_ack_hv_reg(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, unsigned size)
{
return xive_tctx_accept(tctx, TM_QW3_HV_PHYS);
}
-static uint64_t xive_tm_pull_pool_ctx(XiveTCTX *tctx, hwaddr offset,
- unsigned size)
+static uint64_t xive_tm_pull_pool_ctx(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, unsigned size)
{
uint32_t qw2w2_prev = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]);
uint32_t qw2w2;
@@ -166,13 +170,14 @@ static uint64_t xive_tm_pull_pool_ctx(XiveTCTX *tctx, hwaddr offset,
return qw2w2;
}
-static void xive_tm_vt_push(XiveTCTX *tctx, hwaddr offset,
+static void xive_tm_vt_push(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
uint64_t value, unsigned size)
{
tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] = value & 0xff;
}
-static uint64_t xive_tm_vt_poll(XiveTCTX *tctx, hwaddr offset, unsigned size)
+static uint64_t xive_tm_vt_poll(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, unsigned size)
{
return tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] & 0xff;
}
@@ -315,13 +320,14 @@ static uint64_t xive_tm_raw_read(XiveTCTX *tctx, hwaddr offset, unsigned size)
* state changes (side effects) in addition to setting/returning the
* interrupt management area context of the processor thread.
*/
-static uint64_t xive_tm_ack_os_reg(XiveTCTX *tctx, hwaddr offset, unsigned size)
+static uint64_t xive_tm_ack_os_reg(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, unsigned size)
{
return xive_tctx_accept(tctx, TM_QW1_OS);
}
-static void xive_tm_set_os_cppr(XiveTCTX *tctx, hwaddr offset,
- uint64_t value, unsigned size)
+static void xive_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, uint64_t value, unsigned size)
{
xive_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff);
}
@@ -330,24 +336,114 @@ static void xive_tm_set_os_cppr(XiveTCTX *tctx, hwaddr offset,
* Adjust the IPB to allow a CPU to process event queues of other
* priorities during one physical interrupt cycle.
*/
-static void xive_tm_set_os_pending(XiveTCTX *tctx, hwaddr offset,
- uint64_t value, unsigned size)
+static void xive_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, uint64_t value, unsigned size)
{
- ipb_update(&tctx->regs[TM_QW1_OS], value & 0xff);
- xive_tctx_notify(tctx, TM_QW1_OS);
+ xive_tctx_ipb_update(tctx, TM_QW1_OS, priority_to_ipb(value & 0xff));
}
-static uint64_t xive_tm_pull_os_ctx(XiveTCTX *tctx, hwaddr offset,
- unsigned size)
+static void xive_os_cam_decode(uint32_t cam, uint8_t *nvt_blk,
+ uint32_t *nvt_idx, bool *vo)
{
- uint32_t qw1w2_prev = xive_tctx_word2(&tctx->regs[TM_QW1_OS]);
- uint32_t qw1w2;
+ if (nvt_blk) {
+ *nvt_blk = xive_nvt_blk(cam);
+ }
+ if (nvt_idx) {
+ *nvt_idx = xive_nvt_idx(cam);
+ }
+ if (vo) {
+ *vo = !!(cam & TM_QW1W2_VO);
+ }
+}
+
+static uint32_t xive_tctx_get_os_cam(XiveTCTX *tctx, uint8_t *nvt_blk,
+ uint32_t *nvt_idx, bool *vo)
+{
+ uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]);
+ uint32_t cam = be32_to_cpu(qw1w2);
- qw1w2 = xive_set_field32(TM_QW1W2_VO, qw1w2_prev, 0);
+ xive_os_cam_decode(cam, nvt_blk, nvt_idx, vo);
+ return qw1w2;
+}
+
+static void xive_tctx_set_os_cam(XiveTCTX *tctx, uint32_t qw1w2)
+{
memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4);
+}
+
+static uint64_t xive_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, unsigned size)
+{
+ uint32_t qw1w2;
+ uint32_t qw1w2_new;
+ uint8_t nvt_blk;
+ uint32_t nvt_idx;
+ bool vo;
+
+ qw1w2 = xive_tctx_get_os_cam(tctx, &nvt_blk, &nvt_idx, &vo);
+
+ if (!vo) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pulling invalid NVT %x/%x !?\n",
+ nvt_blk, nvt_idx);
+ }
+
+ /* Invalidate CAM line */
+ qw1w2_new = xive_set_field32(TM_QW1W2_VO, qw1w2, 0);
+ xive_tctx_set_os_cam(tctx, qw1w2_new);
return qw1w2;
}
+static void xive_tctx_need_resend(XiveRouter *xrtr, XiveTCTX *tctx,
+ uint8_t nvt_blk, uint32_t nvt_idx)
+{
+ XiveNVT nvt;
+ uint8_t ipb;
+
+ /*
+ * Grab the associated NVT to pull the pending bits, and merge
+ * them with the IPB of the thread interrupt context registers
+ */
+ if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVT %x/%x\n",
+ nvt_blk, nvt_idx);
+ return;
+ }
+
+ ipb = xive_get_field32(NVT_W4_IPB, nvt.w4);
+
+ if (ipb) {
+ /* Reset the NVT value */
+ nvt.w4 = xive_set_field32(NVT_W4_IPB, nvt.w4, 0);
+ xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4);
+
+ /* Merge in current context */
+ xive_tctx_ipb_update(tctx, TM_QW1_OS, ipb);
+ }
+}
+
+/*
+ * Updating the OS CAM line can trigger a resend of interrupt
+ */
+static void xive_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, uint64_t value, unsigned size)
+{
+ uint32_t cam = value;
+ uint32_t qw1w2 = cpu_to_be32(cam);
+ uint8_t nvt_blk;
+ uint32_t nvt_idx;
+ bool vo;
+
+ xive_os_cam_decode(cam, &nvt_blk, &nvt_idx, &vo);
+
+ /* First update the registers */
+ xive_tctx_set_os_cam(tctx, qw1w2);
+
+ /* Check the interrupt pending bits */
+ if (vo) {
+ xive_tctx_need_resend(XIVE_ROUTER(xptr), tctx, nvt_blk, nvt_idx);
+ }
+}
+
/*
* Define a mapping of "special" operations depending on the TIMA page
* offset and the size of the operation.
@@ -356,9 +452,11 @@ typedef struct XiveTmOp {
uint8_t page_offset;
uint32_t op_offset;
unsigned size;
- void (*write_handler)(XiveTCTX *tctx, hwaddr offset, uint64_t value,
- unsigned size);
- uint64_t (*read_handler)(XiveTCTX *tctx, hwaddr offset, unsigned size);
+ void (*write_handler)(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset,
+ uint64_t value, unsigned size);
+ uint64_t (*read_handler)(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
+ unsigned size);
} XiveTmOp;
static const XiveTmOp xive_tm_operations[] = {
@@ -367,6 +465,7 @@ static const XiveTmOp xive_tm_operations[] = {
* effects
*/
{ XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr, NULL },
+ { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, xive_tm_push_os_ctx, NULL },
{ XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, NULL },
{ XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push, NULL },
{ XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL, xive_tm_vt_poll },
@@ -404,8 +503,8 @@ static const XiveTmOp *xive_tm_find_op(hwaddr offset, unsigned size, bool write)
/*
* TIMA MMIO handlers
*/
-void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value,
- unsigned size)
+void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
+ uint64_t value, unsigned size)
{
const XiveTmOp *xto;
@@ -422,7 +521,7 @@ void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value,
qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA "
"@%"HWADDR_PRIx"\n", offset);
} else {
- xto->write_handler(tctx, offset, value, size);
+ xto->write_handler(xptr, tctx, offset, value, size);
}
return;
}
@@ -432,7 +531,7 @@ void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value,
*/
xto = xive_tm_find_op(offset, size, true);
if (xto) {
- xto->write_handler(tctx, offset, value, size);
+ xto->write_handler(xptr, tctx, offset, value, size);
return;
}
@@ -442,7 +541,8 @@ void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value,
xive_tm_raw_write(tctx, offset, value, size);
}
-uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset, unsigned size)
+uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
+ unsigned size)
{
const XiveTmOp *xto;
@@ -460,7 +560,7 @@ uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset, unsigned size)
"@%"HWADDR_PRIx"\n", offset);
return -1;
}
- return xto->read_handler(tctx, offset, size);
+ return xto->read_handler(xptr, tctx, offset, size);
}
/*
@@ -468,7 +568,7 @@ uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset, unsigned size)
*/
xto = xive_tm_find_op(offset, size, false);
if (xto) {
- return xto->read_handler(tctx, offset, size);
+ return xto->read_handler(xptr, tctx, offset, size);
}
/*
@@ -477,35 +577,6 @@ uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset, unsigned size)
return xive_tm_raw_read(tctx, offset, size);
}
-static void xive_tm_write(void *opaque, hwaddr offset,
- uint64_t value, unsigned size)
-{
- XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu);
-
- xive_tctx_tm_write(tctx, offset, value, size);
-}
-
-static uint64_t xive_tm_read(void *opaque, hwaddr offset, unsigned size)
-{
- XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu);
-
- return xive_tctx_tm_read(tctx, offset, size);
-}
-
-const MemoryRegionOps xive_tm_ops = {
- .read = xive_tm_read,
- .write = xive_tm_write,
- .endianness = DEVICE_BIG_ENDIAN,
- .valid = {
- .min_access_size = 1,
- .max_access_size = 8,
- },
- .impl = {
- .min_access_size = 1,
- .max_access_size = 8,
- },
-};
-
static char *xive_tctx_ring_print(uint8_t *ring)
{
uint32_t w2 = xive_tctx_word2(ring);
@@ -580,19 +651,11 @@ static void xive_tctx_realize(DeviceState *dev, Error **errp)
XiveTCTX *tctx = XIVE_TCTX(dev);
PowerPCCPU *cpu;
CPUPPCState *env;
- Object *obj;
Error *local_err = NULL;
- obj = object_property_get_link(OBJECT(dev), "cpu", &local_err);
- if (!obj) {
- error_propagate(errp, local_err);
- error_prepend(errp, "required link 'cpu' not found: ");
- return;
- }
-
- cpu = POWERPC_CPU(obj);
- tctx->cs = CPU(obj);
+ assert(tctx->cs);
+ cpu = POWERPC_CPU(tctx->cs);
env = &cpu->env;
switch (PPC_INPUT(env)) {
case PPC_FLAGS_INPUT_POWER9:
@@ -662,6 +725,11 @@ static const VMStateDescription vmstate_xive_tctx = {
},
};
+static Property xive_tctx_properties[] = {
+ DEFINE_PROP_LINK("cpu", XiveTCTX, cs, TYPE_CPU, CPUState *),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void xive_tctx_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -669,6 +737,7 @@ static void xive_tctx_class_init(ObjectClass *klass, void *data)
dc->desc = "XIVE Interrupt Thread Context";
dc->realize = xive_tctx_realize;
dc->vmsd = &vmstate_xive_tctx;
+ dc->props = xive_tctx_properties;
/*
* Reason: part of XIVE interrupt controller, needs to be wired up
* by xive_tctx_create().
@@ -691,8 +760,7 @@ Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp)
obj = object_new(TYPE_XIVE_TCTX);
object_property_add_child(cpu, TYPE_XIVE_TCTX, obj, &error_abort);
object_unref(obj);
- object_ref(cpu);
- object_property_add_const_link(obj, "cpu", cpu, &error_abort);
+ object_property_set_link(obj, cpu, "cpu", &error_abort);
object_property_set_bool(obj, true, "realized", &local_err);
if (local_err) {
goto error;
@@ -710,7 +778,6 @@ void xive_tctx_destroy(XiveTCTX *tctx)
{
Object *obj = OBJECT(tctx);
- object_unref(object_property_get_link(obj, "cpu", &error_abort));
object_unparent(obj);
}
@@ -1064,17 +1131,8 @@ static void xive_source_reset(void *dev)
static void xive_source_realize(DeviceState *dev, Error **errp)
{
XiveSource *xsrc = XIVE_SOURCE(dev);
- Object *obj;
- Error *local_err = NULL;
- obj = object_property_get_link(OBJECT(dev), "xive", &local_err);
- if (!obj) {
- error_propagate(errp, local_err);
- error_prepend(errp, "required link 'xive' not found: ");
- return;
- }
-
- xsrc->xive = XIVE_NOTIFIER(obj);
+ assert(xsrc->xive);
if (!xsrc->nr_irqs) {
error_setg(errp, "Number of interrupt needs to be greater than 0");
@@ -1120,6 +1178,8 @@ static Property xive_source_properties[] = {
DEFINE_PROP_UINT64("flags", XiveSource, esb_flags, 0),
DEFINE_PROP_UINT32("nr-irqs", XiveSource, nr_irqs, 0),
DEFINE_PROP_UINT32("shift", XiveSource, esb_shift, XIVE_ESB_64K_2PAGE),
+ DEFINE_PROP_LINK("xive", XiveSource, xive, TYPE_XIVE_NOTIFIER,
+ XiveNotifier *),
DEFINE_PROP_END_OF_LIST(),
};
@@ -1311,11 +1371,11 @@ int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number);
}
-XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs)
+static int xive_router_get_block_id(XiveRouter *xrtr)
{
- XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr);
+ XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr);
- return xrc->get_tctx(xrtr, cs);
+ return xrc->get_block_id(xrtr);
}
/*
@@ -1323,20 +1383,22 @@ XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs)
*
* chip << 19 | 0000000 0 0001 thread (7Bit)
*/
-static uint32_t xive_tctx_hw_cam_line(XiveTCTX *tctx)
+static uint32_t xive_tctx_hw_cam_line(XivePresenter *xptr, XiveTCTX *tctx)
{
CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env;
uint32_t pir = env->spr_cb[SPR_PIR].default_value;
+ uint8_t blk = xive_router_get_block_id(XIVE_ROUTER(xptr));
- return xive_nvt_cam_line((pir >> 8) & 0xf, 1 << 7 | (pir & 0x7f));
+ return xive_nvt_cam_line(blk, 1 << 7 | (pir & 0x7f));
}
/*
* The thread context register words are in big-endian format.
*/
-static int xive_presenter_tctx_match(XiveTCTX *tctx, uint8_t format,
- uint8_t nvt_blk, uint32_t nvt_idx,
- bool cam_ignore, uint32_t logic_serv)
+int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
+ uint8_t format,
+ uint8_t nvt_blk, uint32_t nvt_idx,
+ bool cam_ignore, uint32_t logic_serv)
{
uint32_t cam = xive_nvt_cam_line(nvt_blk, nvt_idx);
uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]);
@@ -1364,7 +1426,7 @@ static int xive_presenter_tctx_match(XiveTCTX *tctx, uint8_t format,
/* PHYS ring */
if ((be32_to_cpu(qw3w2) & TM_QW3W2_VT) &&
- cam == xive_tctx_hw_cam_line(tctx)) {
+ cam == xive_tctx_hw_cam_line(xptr, tctx)) {
return TM_QW3_HV_PHYS;
}
@@ -1393,71 +1455,6 @@ static int xive_presenter_tctx_match(XiveTCTX *tctx, uint8_t format,
return -1;
}
-typedef struct XiveTCTXMatch {
- XiveTCTX *tctx;
- uint8_t ring;
-} XiveTCTXMatch;
-
-static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format,
- uint8_t nvt_blk, uint32_t nvt_idx,
- bool cam_ignore, uint8_t priority,
- uint32_t logic_serv, XiveTCTXMatch *match)
-{
- CPUState *cs;
-
- /*
- * TODO (PowerNV): handle chip_id overwrite of block field for
- * hardwired CAM compares
- */
-
- CPU_FOREACH(cs) {
- XiveTCTX *tctx = xive_router_get_tctx(xrtr, cs);
- int ring;
-
- /*
- * Skip partially initialized vCPUs. This can happen when
- * vCPUs are hotplugged.
- */
- if (!tctx) {
- continue;
- }
-
- /*
- * HW checks that the CPU is enabled in the Physical Thread
- * Enable Register (PTER).
- */
-
- /*
- * Check the thread context CAM lines and record matches. We
- * will handle CPU exception delivery later
- */
- ring = xive_presenter_tctx_match(tctx, format, nvt_blk, nvt_idx,
- cam_ignore, logic_serv);
- /*
- * Save the context and follow on to catch duplicates, that we
- * don't support yet.
- */
- if (ring != -1) {
- if (match->tctx) {
- qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a thread "
- "context NVT %x/%x\n", nvt_blk, nvt_idx);
- return false;
- }
-
- match->ring = ring;
- match->tctx = tctx;
- }
- }
-
- if (!match->tctx) {
- qemu_log_mask(LOG_UNIMP, "XIVE: NVT %x/%x is not dispatched\n",
- nvt_blk, nvt_idx);
- return false;
- }
-
- return true;
-}
-
/*
* This is our simple Xive Presenter Engine model. It is merged in the
* Router as it does not require an extra object.
@@ -1473,22 +1470,31 @@ static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format,
*
* The parameters represent what is sent on the PowerBus
*/
-static bool xive_presenter_notify(XiveRouter *xrtr, uint8_t format,
+static bool xive_presenter_notify(uint8_t format,
uint8_t nvt_blk, uint32_t nvt_idx,
bool cam_ignore, uint8_t priority,
uint32_t logic_serv)
{
+ XiveFabric *xfb = XIVE_FABRIC(qdev_get_machine());
+ XiveFabricClass *xfc = XIVE_FABRIC_GET_CLASS(xfb);
XiveTCTXMatch match = { .tctx = NULL, .ring = 0 };
- bool found;
+ int count;
- found = xive_presenter_match(xrtr, format, nvt_blk, nvt_idx, cam_ignore,
- priority, logic_serv, &match);
- if (found) {
- ipb_update(&match.tctx->regs[match.ring], priority);
- xive_tctx_notify(match.tctx, match.ring);
+ /*
+ * Ask the machine to scan the interrupt controllers for a match
+ */
+ count = xfc->match_nvt(xfb, format, nvt_blk, nvt_idx, cam_ignore,
+ priority, logic_serv, &match);
+ if (count < 0) {
+ return false;
}
- return found;
+ /* handle CPU exception delivery */
+ if (count) {
+ xive_tctx_ipb_update(match.tctx, match.ring, priority_to_ipb(priority));
+ }
+
+ return !!count;
}
/*
@@ -1601,7 +1607,7 @@ static void xive_router_end_notify(XiveRouter *xrtr, uint8_t end_blk,
return;
}
- found = xive_presenter_notify(xrtr, format, nvt_blk, nvt_idx,
+ found = xive_presenter_notify(format, nvt_blk, nvt_idx,
xive_get_field32(END_W7_F0_IGNORE, end.w7),
priority,
xive_get_field32(END_W7_F1_LOG_SERVER_ID, end.w7));
@@ -1618,14 +1624,21 @@ static void xive_router_end_notify(XiveRouter *xrtr, uint8_t end_blk,
* - logical server : forward request to IVPE (not supported)
*/
if (xive_end_is_backlog(&end)) {
+ uint8_t ipb;
+
if (format == 1) {
qemu_log_mask(LOG_GUEST_ERROR,
"XIVE: END %x/%x invalid config: F1 & backlog\n",
end_blk, end_idx);
return;
}
- /* Record the IPB in the associated NVT structure */
- ipb_update((uint8_t *) &nvt.w4, priority);
+ /*
+ * Record the IPB in the associated NVT structure for later
+ * use. The presenter will resend the interrupt when the vCPU
+ * is dispatched again on a HW thread.
+ */
+ ipb = xive_get_field32(NVT_W4_IPB, nvt.w4) | priority_to_ipb(priority);
+ nvt.w4 = xive_set_field32(NVT_W4_IPB, nvt.w4, ipb);
xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4);
/*
@@ -1718,6 +1731,7 @@ static const TypeInfo xive_router_info = {
.class_init = xive_router_class_init,
.interfaces = (InterfaceInfo[]) {
{ TYPE_XIVE_NOTIFIER },
+ { TYPE_XIVE_PRESENTER },
{ }
}
};
@@ -1749,7 +1763,11 @@ static uint64_t xive_end_source_read(void *opaque, hwaddr addr, unsigned size)
uint8_t pq;
uint64_t ret = -1;
- end_blk = xsrc->block_id;
+ /*
+ * The block id should be deduced from the load address on the END
+ * ESB MMIO but our model only supports a single block per XIVE chip.
+ */
+ end_blk = xive_router_get_block_id(xsrc->xrtr);
end_idx = addr >> (xsrc->esb_shift + 1);
if (xive_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) {
@@ -1825,17 +1843,8 @@ static const MemoryRegionOps xive_end_source_ops = {
static void xive_end_source_realize(DeviceState *dev, Error **errp)
{
XiveENDSource *xsrc = XIVE_END_SOURCE(dev);
- Object *obj;
- Error *local_err = NULL;
- obj = object_property_get_link(OBJECT(dev), "xive", &local_err);
- if (!obj) {
- error_propagate(errp, local_err);
- error_prepend(errp, "required link 'xive' not found: ");
- return;
- }
-
- xsrc->xrtr = XIVE_ROUTER(obj);
+ assert(xsrc->xrtr);
if (!xsrc->nr_ends) {
error_setg(errp, "Number of interrupt needs to be greater than 0");
@@ -1858,9 +1867,10 @@ static void xive_end_source_realize(DeviceState *dev, Error **errp)
}
static Property xive_end_source_properties[] = {
- DEFINE_PROP_UINT8("block-id", XiveENDSource, block_id, 0),
DEFINE_PROP_UINT32("nr-ends", XiveENDSource, nr_ends, 0),
DEFINE_PROP_UINT32("shift", XiveENDSource, esb_shift, XIVE_ESB_64K),
+ DEFINE_PROP_LINK("xive", XiveENDSource, xrtr, TYPE_XIVE_ROUTER,
+ XiveRouter *),
DEFINE_PROP_END_OF_LIST(),
};
@@ -1894,10 +1904,30 @@ static const TypeInfo xive_notifier_info = {
.class_size = sizeof(XiveNotifierClass),
};
+/*
+ * XIVE Presenter
+ */
+static const TypeInfo xive_presenter_info = {
+ .name = TYPE_XIVE_PRESENTER,
+ .parent = TYPE_INTERFACE,
+ .class_size = sizeof(XivePresenterClass),
+};
+
+/*
+ * XIVE Fabric
+ */
+static const TypeInfo xive_fabric_info = {
+ .name = TYPE_XIVE_FABRIC,
+ .parent = TYPE_INTERFACE,
+ .class_size = sizeof(XiveFabricClass),
+};
+
static void xive_register_types(void)
{
+ type_register_static(&xive_fabric_info);
type_register_static(&xive_source_info);
type_register_static(&xive_notifier_info);
+ type_register_static(&xive_presenter_info);
type_register_static(&xive_router_info);
type_register_static(&xive_end_source_info);
type_register_static(&xive_tctx_info);
generated by cgit v1.1 at 2025-04-03 06:41:44 +0000