diff options
Diffstat (limited to 'hw/intc/xive.c')
-rw-r--r-- | hw/intc/xive.c | 77 |
1 files changed, 70 insertions, 7 deletions
diff --git a/hw/intc/xive.c b/hw/intc/xive.c index f15f985..b8e4c72 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -887,6 +887,16 @@ static bool xive_source_lsi_trigger(XiveSource *xsrc, uint32_t srcno) } /* + * Sources can be configured with PQ offloading in which case the check + * on the PQ state bits of MSIs is disabled + */ +static bool xive_source_esb_disabled(XiveSource *xsrc, uint32_t srcno) +{ + return (xsrc->esb_flags & XIVE_SRC_PQ_DISABLE) && + !xive_source_irq_is_lsi(xsrc, srcno); +} + +/* * Returns whether the event notification should be forwarded. */ static bool xive_source_esb_trigger(XiveSource *xsrc, uint32_t srcno) @@ -895,6 +905,10 @@ static bool xive_source_esb_trigger(XiveSource *xsrc, uint32_t srcno) assert(srcno < xsrc->nr_irqs); + if (xive_source_esb_disabled(xsrc, srcno)) { + return true; + } + ret = xive_esb_trigger(&xsrc->status[srcno]); if (xive_source_irq_is_lsi(xsrc, srcno) && @@ -915,6 +929,11 @@ static bool xive_source_esb_eoi(XiveSource *xsrc, uint32_t srcno) assert(srcno < xsrc->nr_irqs); + if (xive_source_esb_disabled(xsrc, srcno)) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid EOI for IRQ %d\n", srcno); + return false; + } + ret = xive_esb_eoi(&xsrc->status[srcno]); /* @@ -936,9 +955,10 @@ static bool xive_source_esb_eoi(XiveSource *xsrc, uint32_t srcno) static void xive_source_notify(XiveSource *xsrc, int srcno) { XiveNotifierClass *xnc = XIVE_NOTIFIER_GET_CLASS(xsrc->xive); + bool pq_checked = !xive_source_esb_disabled(xsrc, srcno); if (xnc->notify) { - xnc->notify(xsrc->xive, srcno); + xnc->notify(xsrc->xive, srcno, pq_checked); } } @@ -1061,6 +1081,15 @@ static void xive_source_esb_write(void *opaque, hwaddr addr, notify = xive_source_esb_eoi(xsrc, srcno); break; + /* + * This is an internal offset used to inject triggers when the PQ + * state bits are not controlled locally. Such as for LSIs when + * under ABT mode. + */ + case XIVE_ESB_INJECT ... XIVE_ESB_INJECT + 0x3FF: + notify = true; + break; + case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: @@ -1361,6 +1390,24 @@ int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx, return xrc->get_eas(xrtr, eas_blk, eas_idx, eas); } +static +int xive_router_get_pq(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx, + uint8_t *pq) +{ + XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); + + return xrc->get_pq(xrtr, eas_blk, eas_idx, pq); +} + +static +int xive_router_set_pq(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx, + uint8_t *pq) +{ + XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); + + return xrc->set_pq(xrtr, eas_blk, eas_idx, pq); +} + int xive_router_get_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx, XiveEND *end) { @@ -1712,7 +1759,7 @@ do_escalation: xive_get_field32(END_W5_ESC_END_DATA, end.w5)); } -void xive_router_notify(XiveNotifier *xn, uint32_t lisn) +void xive_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked) { XiveRouter *xrtr = XIVE_ROUTER(xn); uint8_t eas_blk = XIVE_EAS_BLOCK(lisn); @@ -1725,11 +1772,27 @@ void xive_router_notify(XiveNotifier *xn, uint32_t lisn) return; } - /* - * The IVRE checks the State Bit Cache at this point. We skip the - * SBC lookup because the state bits of the sources are modeled - * internally in QEMU. - */ + if (!pq_checked) { + bool notify; + uint8_t pq; + + /* PQ cache lookup */ + if (xive_router_get_pq(xrtr, eas_blk, eas_idx, &pq)) { + /* Set FIR */ + g_assert_not_reached(); + } + + notify = xive_esb_trigger(&pq); + + if (xive_router_set_pq(xrtr, eas_blk, eas_idx, &pq)) { + /* Set FIR */ + g_assert_not_reached(); + } + + if (!notify) { + return; + } + } if (!xive_eas_is_valid(&eas)) { qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid LISN %x\n", lisn); |