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-rw-r--r--hw/cxl/cxl-component-utils.c18
-rw-r--r--hw/cxl/cxl-mailbox-utils.c46
2 files changed, 64 insertions, 0 deletions
diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c
index 9457a1b..afc97b1 100644
--- a/hw/cxl/cxl-component-utils.c
+++ b/hw/cxl/cxl-component-utils.c
@@ -252,6 +252,24 @@ void cxl_component_create_dvsec(CXLComponentState *cxl,
/* Configure write masks */
switch (type) {
case PCIE_CXL_DEVICE_DVSEC:
+ /* Cntrl RW Lock - so needs explicit blocking when lock is set */
+ wmask[offset + offsetof(CXLDVSECDevice, ctrl)] = 0xFD;
+ wmask[offset + offsetof(CXLDVSECDevice, ctrl) + 1] = 0x4F;
+ /* Status is RW1CS */
+ wmask[offset + offsetof(CXLDVSECDevice, ctrl2)] = 0x0F;
+ /* Lock is RW Once */
+ wmask[offset + offsetof(CXLDVSECDevice, lock)] = 0x01;
+ /* range1/2_base_high/low is RW Lock */
+ wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi)] = 0xFF;
+ wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi) + 1] = 0xFF;
+ wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi) + 2] = 0xFF;
+ wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi) + 3] = 0xFF;
+ wmask[offset + offsetof(CXLDVSECDevice, range1_base_lo) + 3] = 0xF0;
+ wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi)] = 0xFF;
+ wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi) + 1] = 0xFF;
+ wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi) + 2] = 0xFF;
+ wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi) + 3] = 0xFF;
+ wmask[offset + offsetof(CXLDVSECDevice, range2_base_lo) + 3] = 0xF0;
break;
case NON_CXL_FUNCTION_MAP_DVSEC:
break; /* Not yet implemented */
diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
index db47313..4ae0561 100644
--- a/hw/cxl/cxl-mailbox-utils.c
+++ b/hw/cxl/cxl-mailbox-utils.c
@@ -50,6 +50,8 @@ enum {
LOGS = 0x04,
#define GET_SUPPORTED 0x0
#define GET_LOG 0x1
+ IDENTIFY = 0x40,
+ #define MEMORY_DEVICE 0x0
};
/* 8.2.8.4.5.1 Command Return Codes */
@@ -214,6 +216,48 @@ static ret_code cmd_logs_get_log(struct cxl_cmd *cmd,
return CXL_MBOX_SUCCESS;
}
+/* 8.2.9.5.1.1 */
+static ret_code cmd_identify_memory_device(struct cxl_cmd *cmd,
+ CXLDeviceState *cxl_dstate,
+ uint16_t *len)
+{
+ struct {
+ char fw_revision[0x10];
+ uint64_t total_capacity;
+ uint64_t volatile_capacity;
+ uint64_t persistent_capacity;
+ uint64_t partition_align;
+ uint16_t info_event_log_size;
+ uint16_t warning_event_log_size;
+ uint16_t failure_event_log_size;
+ uint16_t fatal_event_log_size;
+ uint32_t lsa_size;
+ uint8_t poison_list_max_mer[3];
+ uint16_t inject_poison_limit;
+ uint8_t poison_caps;
+ uint8_t qos_telemetry_caps;
+ } QEMU_PACKED *id;
+ QEMU_BUILD_BUG_ON(sizeof(*id) != 0x43);
+
+ uint64_t size = cxl_dstate->pmem_size;
+
+ if (!QEMU_IS_ALIGNED(size, 256 << 20)) {
+ return CXL_MBOX_INTERNAL_ERROR;
+ }
+
+ id = (void *)cmd->payload;
+ memset(id, 0, sizeof(*id));
+
+ /* PMEM only */
+ snprintf(id->fw_revision, 0x10, "BWFW VERSION %02d", 0);
+
+ id->total_capacity = size / (256 << 20);
+ id->persistent_capacity = size / (256 << 20);
+
+ *len = sizeof(*id);
+ return CXL_MBOX_SUCCESS;
+}
+
#define IMMEDIATE_CONFIG_CHANGE (1 << 1)
#define IMMEDIATE_POLICY_CHANGE (1 << 3)
#define IMMEDIATE_LOG_CHANGE (1 << 4)
@@ -231,6 +275,8 @@ static struct cxl_cmd cxl_cmd_set[256][256] = {
[TIMESTAMP][SET] = { "TIMESTAMP_SET", cmd_timestamp_set, 8, IMMEDIATE_POLICY_CHANGE },
[LOGS][GET_SUPPORTED] = { "LOGS_GET_SUPPORTED", cmd_logs_get_supported, 0, 0 },
[LOGS][GET_LOG] = { "LOGS_GET_LOG", cmd_logs_get_log, 0x18, 0 },
+ [IDENTIFY][MEMORY_DEVICE] = { "IDENTIFY_MEMORY_DEVICE",
+ cmd_identify_memory_device, 0, 0 },
};
void cxl_process_mailbox(CXLDeviceState *cxl_dstate)