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-rw-r--r--docs/system/devices/cxl.rst2
-rw-r--r--docs/system/introduction.rst2
2 files changed, 2 insertions, 2 deletions
diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
index f25783a..4c38223 100644
--- a/docs/system/devices/cxl.rst
+++ b/docs/system/devices/cxl.rst
@@ -111,7 +111,7 @@ Interfaces provided include:
CXL Root Ports (CXL RP)
~~~~~~~~~~~~~~~~~~~~~~~
-A CXL Root Port servers te same purpose as a PCIe Root Port.
+A CXL Root Port serves the same purpose as a PCIe Root Port.
There are a number of CXL specific Designated Vendor Specific
Extended Capabilities (DVSEC) in PCIe Configuration Space
and associated component register access via PCI bars.
diff --git a/docs/system/introduction.rst b/docs/system/introduction.rst
index c8a9fe6..3e256f8 100644
--- a/docs/system/introduction.rst
+++ b/docs/system/introduction.rst
@@ -27,7 +27,7 @@ Tiny Code Generator (TCG) capable of emulating many CPUs.
* - Hypervisor Framework (hvf)
- MacOS
- x86 (64 bit only), Arm (64 bit only)
- * - Windows Hypervisor Platform (wphx)
+ * - Windows Hypervisor Platform (whpx)
- Windows
- x86
* - NetBSD Virtual Machine Monitor (nvmm)