aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--crypto/cipher.c5
-rw-r--r--crypto/hash.c13
-rw-r--r--crypto/hmac.c4
-rw-r--r--hw/display/sm501.c2
-rw-r--r--hw/ppc/e500.c32
-rw-r--r--target/ppc/compat.c2
-rw-r--r--tests/test-aio-multithread.c5
-rw-r--r--tests/test-crypto-block.c3
-rw-r--r--util/async.c2
9 files changed, 27 insertions, 41 deletions
diff --git a/crypto/cipher.c b/crypto/cipher.c
index 0aad9d6..bcbfb3d 100644
--- a/crypto/cipher.c
+++ b/crypto/cipher.c
@@ -164,11 +164,10 @@ QCryptoCipher *qcrypto_cipher_new(QCryptoCipherAlgorithm alg,
{
QCryptoCipher *cipher;
void *ctx = NULL;
- Error *err2 = NULL;
QCryptoCipherDriver *drv = NULL;
#ifdef CONFIG_AF_ALG
- ctx = qcrypto_afalg_cipher_ctx_new(alg, mode, key, nkey, &err2);
+ ctx = qcrypto_afalg_cipher_ctx_new(alg, mode, key, nkey, NULL);
if (ctx) {
drv = &qcrypto_cipher_afalg_driver;
}
@@ -177,12 +176,10 @@ QCryptoCipher *qcrypto_cipher_new(QCryptoCipherAlgorithm alg,
if (!ctx) {
ctx = qcrypto_cipher_ctx_new(alg, mode, key, nkey, errp);
if (!ctx) {
- error_free(err2);
return NULL;
}
drv = &qcrypto_cipher_lib_driver;
- error_free(err2);
}
cipher = g_new0(QCryptoCipher, 1);
diff --git a/crypto/hash.c b/crypto/hash.c
index ac59c63..8dab25d 100644
--- a/crypto/hash.c
+++ b/crypto/hash.c
@@ -48,19 +48,16 @@ int qcrypto_hash_bytesv(QCryptoHashAlgorithm alg,
{
#ifdef CONFIG_AF_ALG
int ret;
-
+ /*
+ * TODO:
+ * Maybe we should treat some afalg errors as fatal
+ */
ret = qcrypto_hash_afalg_driver.hash_bytesv(alg, iov, niov,
result, resultlen,
- errp);
+ NULL);
if (ret == 0) {
return ret;
}
-
- /*
- * TODO:
- * Maybe we should treat some afalg errors as fatal
- */
- error_free(*errp);
#endif
return qcrypto_hash_lib_driver.hash_bytesv(alg, iov, niov,
diff --git a/crypto/hmac.c b/crypto/hmac.c
index 82b0055..f6c2d8d 100644
--- a/crypto/hmac.c
+++ b/crypto/hmac.c
@@ -90,11 +90,10 @@ QCryptoHmac *qcrypto_hmac_new(QCryptoHashAlgorithm alg,
{
QCryptoHmac *hmac;
void *ctx = NULL;
- Error *err2 = NULL;
QCryptoHmacDriver *drv = NULL;
#ifdef CONFIG_AF_ALG
- ctx = qcrypto_afalg_hmac_ctx_new(alg, key, nkey, &err2);
+ ctx = qcrypto_afalg_hmac_ctx_new(alg, key, nkey, NULL);
if (ctx) {
drv = &qcrypto_hmac_afalg_driver;
}
@@ -107,7 +106,6 @@ QCryptoHmac *qcrypto_hmac_new(QCryptoHashAlgorithm alg,
}
drv = &qcrypto_hmac_lib_driver;
- error_free(err2);
}
hmac = g_new0(QCryptoHmac, 1);
diff --git a/hw/display/sm501.c b/hw/display/sm501.c
index 6eddac9..7f18224 100644
--- a/hw/display/sm501.c
+++ b/hw/display/sm501.c
@@ -1758,7 +1758,7 @@ static void sm501_sysbus_class_init(ObjectClass *klass, void *data)
dc->reset = sm501_reset_sysbus;
dc->vmsd = &vmstate_sm501_sysbus;
/* Note: pointer property "chr-state" may remain null, thus
- * no need for dc->cannot_instantiate_with_device_add_yet = true;
+ * no need for dc->user_creatable = false;
*/
}
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index 9178e70..5cf0dab 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -729,15 +729,13 @@ static DeviceState *ppce500_init_mpic_kvm(PPCE500Params *params,
return dev;
}
-static qemu_irq *ppce500_init_mpic(MachineState *machine, PPCE500Params *params,
- MemoryRegion *ccsr, qemu_irq **irqs)
+static DeviceState *ppce500_init_mpic(MachineState *machine,
+ PPCE500Params *params,
+ MemoryRegion *ccsr,
+ qemu_irq **irqs)
{
- qemu_irq *mpic;
DeviceState *dev = NULL;
SysBusDevice *s;
- int i;
-
- mpic = g_new0(qemu_irq, 256);
if (kvm_enabled()) {
Error *err = NULL;
@@ -756,15 +754,11 @@ static qemu_irq *ppce500_init_mpic(MachineState *machine, PPCE500Params *params,
dev = ppce500_init_mpic_qemu(params, irqs);
}
- for (i = 0; i < 256; i++) {
- mpic[i] = qdev_get_gpio_in(dev, i);
- }
-
s = SYS_BUS_DEVICE(dev);
memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET,
s->mmio[0].memory);
- return mpic;
+ return dev;
}
static void ppce500_power_off(void *opaque, int line, int on)
@@ -796,8 +790,8 @@ void ppce500_init(MachineState *machine, PPCE500Params *params)
/* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and
* 4 respectively */
unsigned int pci_irq_nrs[PCI_NUM_PINS] = {1, 2, 3, 4};
- qemu_irq **irqs, *mpic;
- DeviceState *dev;
+ qemu_irq **irqs;
+ DeviceState *dev, *mpicdev;
CPUPPCState *firstenv = NULL;
MemoryRegion *ccsr_addr_space;
SysBusDevice *s;
@@ -866,18 +860,18 @@ void ppce500_init(MachineState *machine, PPCE500Params *params)
memory_region_add_subregion(address_space_mem, params->ccsrbar_base,
ccsr_addr_space);
- mpic = ppce500_init_mpic(machine, params, ccsr_addr_space, irqs);
+ mpicdev = ppce500_init_mpic(machine, params, ccsr_addr_space, irqs);
/* Serial */
if (serial_hds[0]) {
serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET,
- 0, mpic[42], 399193,
+ 0, qdev_get_gpio_in(mpicdev, 42), 399193,
serial_hds[0], DEVICE_BIG_ENDIAN);
}
if (serial_hds[1]) {
serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET,
- 0, mpic[42], 399193,
+ 0, qdev_get_gpio_in(mpicdev, 42), 399193,
serial_hds[1], DEVICE_BIG_ENDIAN);
}
@@ -895,7 +889,7 @@ void ppce500_init(MachineState *machine, PPCE500Params *params)
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
for (i = 0; i < PCI_NUM_PINS; i++) {
- sysbus_connect_irq(s, i, mpic[pci_irq_nrs[i]]);
+ sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, pci_irq_nrs[i]));
}
memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET,
@@ -926,7 +920,7 @@ void ppce500_init(MachineState *machine, PPCE500Params *params)
dev = qdev_create(NULL, "mpc8xxx_gpio");
s = SYS_BUS_DEVICE(dev);
qdev_init_nofail(dev);
- sysbus_connect_irq(s, 0, mpic[MPC8XXX_GPIO_IRQ]);
+ sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8XXX_GPIO_IRQ));
memory_region_add_subregion(ccsr_addr_space, MPC8XXX_GPIO_OFFSET,
sysbus_mmio_get_region(s, 0));
@@ -946,7 +940,7 @@ void ppce500_init(MachineState *machine, PPCE500Params *params)
for (i = 0; i < params->platform_bus_num_irqs; i++) {
int irqn = params->platform_bus_first_irq + i;
- sysbus_connect_irq(s, i, mpic[irqn]);
+ sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, irqn));
}
memory_region_add_subregion(address_space_mem,
diff --git a/target/ppc/compat.c b/target/ppc/compat.c
index f8729fe..ad8f93c 100644
--- a/target/ppc/compat.c
+++ b/target/ppc/compat.c
@@ -141,7 +141,7 @@ void ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp)
cpu_synchronize_state(CPU(cpu));
if (kvm_enabled() && cpu->compat_pvr != compat_pvr) {
- int ret = kvmppc_set_compat(cpu, cpu->compat_pvr);
+ int ret = kvmppc_set_compat(cpu, compat_pvr);
if (ret < 0) {
error_setg_errno(errp, -ret,
"Unable to set CPU compatibility mode in KVM");
diff --git a/tests/test-aio-multithread.c b/tests/test-aio-multithread.c
index 549d784..d396185 100644
--- a/tests/test-aio-multithread.c
+++ b/tests/test-aio-multithread.c
@@ -144,17 +144,16 @@ static void finish_cb(void *opaque)
static coroutine_fn void test_multi_co_schedule_entry(void *opaque)
{
g_assert(to_schedule[id] == NULL);
- atomic_mb_set(&to_schedule[id], qemu_coroutine_self());
while (!atomic_mb_read(&now_stopping)) {
int n;
n = g_test_rand_int_range(0, NUM_CONTEXTS);
schedule_next(n);
- qemu_coroutine_yield();
- g_assert(to_schedule[id] == NULL);
atomic_mb_set(&to_schedule[id], qemu_coroutine_self());
+ qemu_coroutine_yield();
+ g_assert(to_schedule[id] == NULL);
}
}
diff --git a/tests/test-crypto-block.c b/tests/test-crypto-block.c
index bd7fe59..fd29a04 100644
--- a/tests/test-crypto-block.c
+++ b/tests/test-crypto-block.c
@@ -28,7 +28,8 @@
#include <sys/resource.h>
#endif
-#if (defined(_WIN32) || defined RUSAGE_THREAD)
+#if (defined(_WIN32) || defined RUSAGE_THREAD) && \
+ (defined(CONFIG_NETTLE_KDF) || defined(CONFIG_GCRYPT_KDF))
#define TEST_LUKS
#else
#undef TEST_LUKS
diff --git a/util/async.c b/util/async.c
index 355af73..0e1bd87 100644
--- a/util/async.c
+++ b/util/async.c
@@ -174,7 +174,7 @@ void qemu_bh_schedule(QEMUBH *bh)
*/
void qemu_bh_cancel(QEMUBH *bh)
{
- bh->scheduled = 0;
+ atomic_mb_set(&bh->scheduled, 0);
}
/* This func is async.The bottom half will do the delete action at the finial
generated by cgit v1.1 at 2025-01-06 05:51:47 +0000