diff options
| -rw-r--r-- | Makefile.target | 1 | ||||
| -rw-r--r-- | hw/lm32_pic.c | 190 | ||||
| -rw-r--r-- | hw/lm32_pic.h | 11 | ||||
| -rw-r--r-- | trace-events | 9 |
4 files changed, 211 insertions, 0 deletions
diff --git a/Makefile.target b/Makefile.target index 857976a..a6e7e5a 100644 --- a/Makefile.target +++ b/Makefile.target @@ -248,6 +248,7 @@ obj-ppc-y += xilinx_uartlite.o obj-ppc-y += xilinx_ethlite.o # LM32 peripherals +obj-lm32-y += lm32_pic.o obj-mips-y = mips_r4k.o mips_jazz.o mips_malta.o mips_mipssim.o obj-mips-y += mips_addr.o mips_timer.o mips_int.o diff --git a/hw/lm32_pic.c b/hw/lm32_pic.c new file mode 100644 index 0000000..02941a7 --- /dev/null +++ b/hw/lm32_pic.c @@ -0,0 +1,190 @@ +/* + * LatticeMico32 CPU interrupt controller logic. + * + * Copyright (c) 2010 Michael Walle <michael@walle.cc> + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see <http://www.gnu.org/licenses/>. + */ + +#include <assert.h> + +#include "hw.h" +#include "pc.h" +#include "monitor.h" +#include "sysbus.h" +#include "trace.h" +#include "lm32_pic.h" + +struct LM32PicState { + SysBusDevice busdev; + qemu_irq parent_irq; + uint32_t im; /* interrupt mask */ + uint32_t ip; /* interrupt pending */ + uint32_t irq_state; + + /* statistics */ + uint32_t stats_irq_count[32]; +}; +typedef struct LM32PicState LM32PicState; + +static LM32PicState *pic; +void pic_info(Monitor *mon) +{ + if (pic == NULL) { + return; + } + + monitor_printf(mon, "lm32-pic: im=%08x ip=%08x irq_state=%08x\n", + pic->im, pic->ip, pic->irq_state); +} + +void irq_info(Monitor *mon) +{ + int i; + uint32_t count; + + if (pic == NULL) { + return; + } + + monitor_printf(mon, "IRQ statistics:\n"); + for (i = 0; i < 32; i++) { + count = pic->stats_irq_count[i]; + if (count > 0) { + monitor_printf(mon, "%2d: %u\n", i, count); + } + } +} + +static void update_irq(LM32PicState *s) +{ + s->ip |= s->irq_state; + + if (s->ip & s->im) { + trace_lm32_pic_raise_irq(); + qemu_irq_raise(s->parent_irq); + } else { + trace_lm32_pic_lower_irq(); + qemu_irq_lower(s->parent_irq); + } +} + +static void irq_handler(void *opaque, int irq, int level) +{ + LM32PicState *s = opaque; + + assert(irq < 32); + trace_lm32_pic_interrupt(irq, level); + + if (level) { + s->irq_state |= (1 << irq); + s->stats_irq_count[irq]++; + } else { + s->irq_state &= ~(1 << irq); + } + + update_irq(s); +} + +void lm32_pic_set_im(DeviceState *d, uint32_t im) +{ + LM32PicState *s = container_of(d, LM32PicState, busdev.qdev); + + trace_lm32_pic_set_im(im); + s->im = im; + + update_irq(s); +} + +void lm32_pic_set_ip(DeviceState *d, uint32_t ip) +{ + LM32PicState *s = container_of(d, LM32PicState, busdev.qdev); + + trace_lm32_pic_set_ip(ip); + + /* ack interrupt */ + s->ip &= ~ip; + + update_irq(s); +} + +uint32_t lm32_pic_get_im(DeviceState *d) +{ + LM32PicState *s = container_of(d, LM32PicState, busdev.qdev); + + trace_lm32_pic_get_im(s->im); + return s->im; +} + +uint32_t lm32_pic_get_ip(DeviceState *d) +{ + LM32PicState *s = container_of(d, LM32PicState, busdev.qdev); + + trace_lm32_pic_get_ip(s->ip); + return s->ip; +} + +static void pic_reset(DeviceState *d) +{ + LM32PicState *s = container_of(d, LM32PicState, busdev.qdev); + int i; + + s->im = 0; + s->ip = 0; + s->irq_state = 0; + for (i = 0; i < 32; i++) { + s->stats_irq_count[i] = 0; + } +} + +static int lm32_pic_init(SysBusDevice *dev) +{ + LM32PicState *s = FROM_SYSBUS(typeof(*s), dev); + + qdev_init_gpio_in(&dev->qdev, irq_handler, 32); + sysbus_init_irq(dev, &s->parent_irq); + + pic = s; + + return 0; +} + +static const VMStateDescription vmstate_lm32_pic = { + .name = "lm32-pic", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(im, LM32PicState), + VMSTATE_UINT32(ip, LM32PicState), + VMSTATE_UINT32(irq_state, LM32PicState), + VMSTATE_UINT32_ARRAY(stats_irq_count, LM32PicState, 32), + VMSTATE_END_OF_LIST() + } +}; + +static SysBusDeviceInfo lm32_pic_info = { + .init = lm32_pic_init, + .qdev.name = "lm32-pic", + .qdev.size = sizeof(LM32PicState), + .qdev.vmsd = &vmstate_lm32_pic, + .qdev.reset = pic_reset, +}; + +static void lm32_pic_register(void) +{ + sysbus_register_withprop(&lm32_pic_info); +} + +device_init(lm32_pic_register) diff --git a/hw/lm32_pic.h b/hw/lm32_pic.h new file mode 100644 index 0000000..e6479b8 --- /dev/null +++ b/hw/lm32_pic.h @@ -0,0 +1,11 @@ +#ifndef QEMU_HW_LM32_PIC_H +#define QEMU_HW_LM32_PIC_H + +#include "qemu-common.h" + +uint32_t lm32_pic_get_ip(DeviceState *d); +uint32_t lm32_pic_get_im(DeviceState *d); +void lm32_pic_set_ip(DeviceState *d, uint32_t ip); +void lm32_pic_set_im(DeviceState *d, uint32_t im); + +#endif /* QEMU_HW_LM32_PIC_H */ diff --git a/trace-events b/trace-events index e6138ea..557375e 100644 --- a/trace-events +++ b/trace-events @@ -254,3 +254,12 @@ disable spice_vmc_write(ssize_t out, int len) "spice wrottn %lu of requested %zd disable spice_vmc_read(int bytes, int len) "spice read %lu of requested %zd" disable spice_vmc_register_interface(void *scd) "spice vmc registered interface %p" disable spice_vmc_unregister_interface(void *scd) "spice vmc unregistered interface %p" + +# hw/lm32_pic.c +disable lm32_pic_raise_irq(void) "Raise CPU interrupt" +disable lm32_pic_lower_irq(void) "Lower CPU interrupt" +disable lm32_pic_interrupt(int irq, int level) "Set IRQ%d %d" +disable lm32_pic_set_im(uint32_t im) "im 0x%08x" +disable lm32_pic_set_ip(uint32_t ip) "ip 0x%08x" +disable lm32_pic_get_im(uint32_t im) "im 0x%08x" +disable lm32_pic_get_ip(uint32_t ip) "ip 0x%08x" |