diff options
| -rw-r--r-- | target/arm/cpu.h | 2 | ||||
| -rw-r--r-- | target/arm/helper.c | 5 |
2 files changed, 6 insertions, 1 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a81f3d8..62c36b4 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1269,7 +1269,7 @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val); * we store the underlying state in fpscr and just mask on read/write. */ #define FPSR_MASK 0xf800009f -#define FPCR_MASK 0x07f79f00 +#define FPCR_MASK 0x07ff9f00 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 873a0c2..0fc6d2e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11349,6 +11349,11 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) int i; uint32_t changed; + /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */ + if (!arm_feature(env, ARM_FEATURE_V8_FP16)) { + val &= ~FPCR_FZ16; + } + changed = env->vfp.xregs[ARM_VFP_FPSCR]; env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff); env->vfp.vec_len = (val >> 16) & 7; |