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-rw-r--r--docs/system/deprecated.rst6
-rw-r--r--hw/core/machine.c12
-rw-r--r--hw/i386/fw_cfg.c2
-rw-r--r--hw/i386/kvm/apic.c5
-rw-r--r--hw/i386/kvm/ioapic.c33
-rw-r--r--hw/i386/microvm.c2
-rw-r--r--hw/i386/pc.c2
-rw-r--r--include/hw/core/cpu.h3
-rw-r--r--include/sysemu/kvm.h19
-rw-r--r--qapi/machine-target.json7
-rw-r--r--target/i386/cpu.c32
-rw-r--r--target/i386/kvm-stub.c5
-rw-r--r--target/i386/kvm.c19
-rw-r--r--target/i386/kvm_i386.h1
14 files changed, 84 insertions, 64 deletions
diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst
index 2ac3bfd..905628f 100644
--- a/docs/system/deprecated.rst
+++ b/docs/system/deprecated.rst
@@ -314,6 +314,12 @@ a future version of QEMU. Support for this CPU was removed from the
upstream Linux kernel, and there is no available upstream toolchain
to build binaries for it.
+``Icelake-Client`` CPU Model (since 5.2.0)
+''''''''''''''''''''''''''''''''''''''''''
+
+``Icelake-Client`` CPU Models are deprecated. Use ``Icelake-Server`` CPU
+Models instead.
+
System emulator devices
-----------------------
diff --git a/hw/core/machine.c b/hw/core/machine.c
index 7e2f4ec..d740a7e 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -1087,6 +1087,8 @@ MemoryRegion *machine_consume_memdev(MachineState *machine,
void machine_run_board_init(MachineState *machine)
{
MachineClass *machine_class = MACHINE_GET_CLASS(machine);
+ ObjectClass *oc = object_class_by_name(machine->cpu_type);
+ CPUClass *cc;
if (machine->ram_memdev_id) {
Object *o;
@@ -1106,11 +1108,10 @@ void machine_run_board_init(MachineState *machine)
* specified a CPU with -cpu check here that the user CPU is supported.
*/
if (machine_class->valid_cpu_types && machine->cpu_type) {
- ObjectClass *class = object_class_by_name(machine->cpu_type);
int i;
for (i = 0; machine_class->valid_cpu_types[i]; i++) {
- if (object_class_dynamic_cast(class,
+ if (object_class_dynamic_cast(oc,
machine_class->valid_cpu_types[i])) {
/* The user specificed CPU is in the valid field, we are
* good to go.
@@ -1133,6 +1134,13 @@ void machine_run_board_init(MachineState *machine)
}
}
+ /* Check if CPU type is deprecated and warn if so */
+ cc = CPU_CLASS(oc);
+ if (cc && cc->deprecation_note) {
+ warn_report("CPU model %s is deprecated -- %s", machine->cpu_type,
+ cc->deprecation_note);
+ }
+
machine_class->init(machine);
}
diff --git a/hw/i386/fw_cfg.c b/hw/i386/fw_cfg.c
index 33441ad..e065794 100644
--- a/hw/i386/fw_cfg.c
+++ b/hw/i386/fw_cfg.c
@@ -123,7 +123,7 @@ FWCfgState *fw_cfg_arch_create(MachineState *ms,
fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
acpi_tables, acpi_tables_len);
#endif
- fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
+ fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, 1);
fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
&e820_reserve, sizeof(e820_reserve));
diff --git a/hw/i386/kvm/apic.c b/hw/i386/kvm/apic.c
index 4eb2d77..dd29906 100644
--- a/hw/i386/kvm/apic.c
+++ b/hw/i386/kvm/apic.c
@@ -225,9 +225,8 @@ static void kvm_apic_realize(DeviceState *dev, Error **errp)
memory_region_init_io(&s->io_memory, OBJECT(s), &kvm_apic_io_ops, s,
"kvm-apic-msi", APIC_SPACE_SIZE);
- if (kvm_has_gsi_routing()) {
- msi_nonbroken = true;
- }
+ assert(kvm_has_gsi_routing());
+ msi_nonbroken = true;
}
static void kvm_apic_unrealize(DeviceState *dev)
diff --git a/hw/i386/kvm/ioapic.c b/hw/i386/kvm/ioapic.c
index c5528df..dfc3c98 100644
--- a/hw/i386/kvm/ioapic.c
+++ b/hw/i386/kvm/ioapic.c
@@ -25,27 +25,26 @@ void kvm_pc_setup_irq_routing(bool pci_enabled)
KVMState *s = kvm_state;
int i;
- if (kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
- for (i = 0; i < 8; ++i) {
- if (i == 2) {
- continue;
- }
- kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_PIC_MASTER, i);
- }
- for (i = 8; i < 16; ++i) {
- kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_PIC_SLAVE, i - 8);
+ assert(kvm_has_gsi_routing());
+ for (i = 0; i < 8; ++i) {
+ if (i == 2) {
+ continue;
}
- if (pci_enabled) {
- for (i = 0; i < 24; ++i) {
- if (i == 0) {
- kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_IOAPIC, 2);
- } else if (i != 2) {
- kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_IOAPIC, i);
- }
+ kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_PIC_MASTER, i);
+ }
+ for (i = 8; i < 16; ++i) {
+ kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_PIC_SLAVE, i - 8);
+ }
+ if (pci_enabled) {
+ for (i = 0; i < 24; ++i) {
+ if (i == 0) {
+ kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_IOAPIC, 2);
+ } else if (i != 2) {
+ kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_IOAPIC, i);
}
}
- kvm_irqchip_commit_routes(s);
}
+ kvm_irqchip_commit_routes(s);
}
typedef struct KVMIOAPICState KVMIOAPICState;
diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c
index 73a7a14..68a7f42 100644
--- a/hw/i386/microvm.c
+++ b/hw/i386/microvm.c
@@ -290,7 +290,7 @@ static void microvm_memory_init(MicrovmMachineState *mms)
fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, machine->smp.cpus);
fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, machine->smp.max_cpus);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
- fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
+ fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, 1);
fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
&e820_reserve, sizeof(e820_reserve));
fw_cfg_add_file(fw_cfg, "etc/e820", e820_table,
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index e87be5d..4e32375 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -827,7 +827,7 @@ void pc_guest_info_init(PCMachineState *pcms)
MachineState *ms = MACHINE(pcms);
X86MachineState *x86ms = X86_MACHINE(pcms);
- x86ms->apic_xrupt_override = kvm_allows_irq0_override();
+ x86ms->apic_xrupt_override = true;
pcms->numa_nodes = ms->numa_state->num_nodes;
pcms->node_mem = g_malloc0(pcms->numa_nodes *
sizeof *pcms->node_mem);
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 4879f250..9c3a45a 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -155,6 +155,8 @@ struct TranslationBlock;
* @disas_set_info: Setup architecture specific components of disassembly info
* @adjust_watchpoint_address: Perform a target-specific adjustment to an
* address before attempting to match it against watchpoints.
+ * @deprecation_note: If this CPUClass is deprecated, this field provides
+ * related information.
*
* Represents a CPU family or model.
*/
@@ -221,6 +223,7 @@ struct CPUClass {
vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
void (*tcg_initialize)(void);
+ const char *deprecation_note;
/* Keep non-pointer data at the end to minimize holes. */
int gdb_num_core_regs;
bool gdb_stop_before_watchpoint;
diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
index fe7dab1..bb5d5cf 100644
--- a/include/sysemu/kvm.h
+++ b/include/sysemu/kvm.h
@@ -51,23 +51,22 @@ extern bool kvm_msi_use_devid;
/**
* kvm_irqchip_in_kernel:
*
- * Returns: true if the user asked us to create an in-kernel
- * irqchip via the "kernel_irqchip=on" machine option.
+ * Returns: true if an in-kernel irqchip was created.
* What this actually means is architecture and machine model
- * specific: on PC, for instance, it means that the LAPIC,
- * IOAPIC and PIT are all in kernel. This function should never
- * be used from generic target-independent code: use one of the
- * following functions or some other specific check instead.
+ * specific: on PC, for instance, it means that the LAPIC
+ * is in kernel. This function should never be used from generic
+ * target-independent code: use one of the following functions or
+ * some other specific check instead.
*/
#define kvm_irqchip_in_kernel() (kvm_kernel_irqchip)
/**
* kvm_irqchip_is_split:
*
- * Returns: true if the user asked us to split the irqchip
- * implementation between user and kernel space. The details are
- * architecture and machine specific. On PC, it means that the PIC,
- * IOAPIC, and PIT are in user space while the LAPIC is in the kernel.
+ * Returns: true if the irqchip implementation is split between
+ * user and kernel space. The details are architecture and
+ * machine specific. On PC, it means that the PIC, IOAPIC, and
+ * PIT are in user space while the LAPIC is in the kernel.
*/
#define kvm_irqchip_is_split() (kvm_split_irqchip)
diff --git a/qapi/machine-target.json b/qapi/machine-target.json
index 698850c..fec3bb8 100644
--- a/qapi/machine-target.json
+++ b/qapi/machine-target.json
@@ -286,6 +286,10 @@
# in the VM configuration, because aliases may stop being
# migration-safe in the future (since 4.1)
#
+# @deprecated: If true, this CPU model is deprecated and may be removed in
+# in some future version of QEMU according to the QEMU deprecation
+# policy. (since 5.2)
+#
# @unavailable-features is a list of QOM property names that
# represent CPU model attributes that prevent the CPU from running.
# If the QOM property is read-only, that means there's no known
@@ -310,7 +314,8 @@
'static': 'bool',
'*unavailable-features': [ 'str' ],
'typename': 'str',
- '*alias-of' : 'str' },
+ '*alias-of' : 'str',
+ 'deprecated' : 'bool' },
'if': 'defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_I386) || defined(TARGET_S390X) || defined(TARGET_MIPS)' }
##
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 5d713c8..0d86069 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1633,6 +1633,7 @@ typedef struct X86CPUDefinition {
* If NULL, version 1 will be registered automatically.
*/
const X86CPUVersionDefinition *versions;
+ const char *deprecation_note;
} X86CPUDefinition;
/* Reference to a specific CPU model version */
@@ -3357,10 +3358,13 @@ static X86CPUDefinition builtin_x86_defs[] = {
.xlevel = 0x80000008,
.model_id = "Intel Core Processor (Icelake)",
.versions = (X86CPUVersionDefinition[]) {
- { .version = 1 },
+ {
+ .version = 1,
+ .note = "deprecated"
+ },
{
.version = 2,
- .note = "no TSX",
+ .note = "no TSX, deprecated",
.alias = "Icelake-Client-noTSX",
.props = (PropValue[]) {
{ "hle", "off" },
@@ -3369,7 +3373,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
},
},
{ /* end of list */ }
- }
+ },
+ .deprecation_note = "use Icelake-Server instead"
},
{
.name = "Icelake-Server",
@@ -4180,9 +4185,6 @@ void x86_cpu_change_kvm_default(const char *prop, const char *value)
assert(pv->prop);
}
-static uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
- bool migratable_only);
-
static bool lmce_supported(void)
{
uint64_t mce_cap = 0;
@@ -4993,6 +4995,11 @@ static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
info->migration_safe = cc->migration_safe;
info->has_migration_safe = true;
info->q_static = cc->static_model;
+ if (cc->model && cc->model->cpudef->deprecation_note) {
+ info->deprecated = true;
+ } else {
+ info->deprecated = false;
+ }
/*
* Old machine types won't report aliases, so that alias translation
* doesn't break compatibility with previous QEMU versions.
@@ -5383,9 +5390,11 @@ static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
{
X86CPUModel *model = data;
X86CPUClass *xcc = X86_CPU_CLASS(oc);
+ CPUClass *cc = CPU_CLASS(oc);
xcc->model = model;
xcc->migration_safe = true;
+ cc->deprecation_note = model->cpudef->deprecation_note;
}
static void x86_register_cpu_model_type(const char *name, X86CPUModel *model)
@@ -5913,9 +5922,14 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
}
break;
case 0x8000001E:
- assert(cpu->core_id <= 255);
- encode_topo_cpuid8000001e(cpu, &topo_info,
- eax, ebx, ecx, edx);
+ if (cpu->core_id <= 255) {
+ encode_topo_cpuid8000001e(cpu, &topo_info, eax, ebx, ecx, edx);
+ } else {
+ *eax = 0;
+ *ebx = 0;
+ *ecx = 0;
+ *edx = 0;
+ }
break;
case 0xC0000000:
*eax = env->cpuid_xlevel2;
diff --git a/target/i386/kvm-stub.c b/target/i386/kvm-stub.c
index 872ef7d..92f4912 100644
--- a/target/i386/kvm-stub.c
+++ b/target/i386/kvm-stub.c
@@ -13,11 +13,6 @@
#include "cpu.h"
#include "kvm_i386.h"
-bool kvm_allows_irq0_override(void)
-{
- return 1;
-}
-
#ifndef __OPTIMIZE__
bool kvm_has_smm(void)
{
diff --git a/target/i386/kvm.c b/target/i386/kvm.c
index 8b12387..cf46259 100644
--- a/target/i386/kvm.c
+++ b/target/i386/kvm.c
@@ -154,11 +154,6 @@ bool kvm_has_exception_payload(void)
return has_exception_payload;
}
-bool kvm_allows_irq0_override(void)
-{
- return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
-}
-
static bool kvm_x2apic_api_set_flags(uint64_t flags)
{
KVMState *s = KVM_STATE(current_accel());
@@ -1214,7 +1209,7 @@ static int hyperv_handle_properties(CPUState *cs,
if (c) {
env->features[FEAT_HYPERV_EAX] = c->eax;
env->features[FEAT_HYPERV_EBX] = c->ebx;
- env->features[FEAT_HYPERV_EDX] = c->eax;
+ env->features[FEAT_HYPERV_EDX] = c->edx;
}
c = cpuid_find_entry(cpuid, HV_CPUID_ENLIGHTMENT_INFO, 0);
if (c) {
@@ -2114,6 +2109,11 @@ int kvm_arch_init(MachineState *ms, KVMState *s)
int ret;
struct utsname utsname;
+ if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
+ error_report("kvm: KVM_CAP_IRQ_ROUTING not supported by KVM");
+ return -ENOTSUP;
+ }
+
has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
@@ -4547,13 +4547,6 @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs)
void kvm_arch_init_irq_routing(KVMState *s)
{
- if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
- /* If kernel can't do irq routing, interrupt source
- * override 0->2 cannot be set up as required by HPET.
- * So we have to disable it.
- */
- no_hpet = 1;
- }
/* We know at this point that we're using the in-kernel
* irqchip, so we can use irqfds, and on x86 we know
* we can use msi via irqfd and GSI routing.
diff --git a/target/i386/kvm_i386.h b/target/i386/kvm_i386.h
index 0fce4e5..a4a619c 100644
--- a/target/i386/kvm_i386.h
+++ b/target/i386/kvm_i386.h
@@ -32,7 +32,6 @@
#endif /* CONFIG_KVM */
-bool kvm_allows_irq0_override(void);
bool kvm_has_smm(void);
bool kvm_has_adjust_clock(void);
bool kvm_has_adjust_clock_stable(void);
generated by cgit v1.1 at 2024-12-24 02:29:28 +0000