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-rw-r--r--target/riscv/debug.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index 2f2a51c..fc6e132 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -77,6 +77,7 @@ static inline target_ulong trigger_type(CPURISCVState *env,
tdata1 = RV32_TYPE(type);
break;
case MXL_RV64:
+ case MXL_RV128:
tdata1 = RV64_TYPE(type);
break;
default:
@@ -123,6 +124,7 @@ static target_ulong tdata1_validate(CPURISCVState *env, target_ulong val,
tdata1 = RV32_TYPE(t);
break;
case MXL_RV64:
+ case MXL_RV128:
type = extract64(val, 60, 4);
dmode = extract64(val, 59, 1);
tdata1 = RV64_TYPE(t);