diff options
| -rw-r--r-- | target/riscv/cpu_helper.c | 6 | ||||
| -rw-r--r-- | target/riscv/internals.h | 9 |
2 files changed, 10 insertions, 5 deletions
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 29ee9b1..57bb19c 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -758,7 +758,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, */ MemTxResult res; MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; - int mode = env->priv; + int mode = mmuidx_priv(mmu_idx); bool use_background = false; hwaddr ppn; int napot_bits = 0; @@ -781,10 +781,6 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, */ if (riscv_cpu_two_stage_lookup(mmu_idx)) { mode = get_field(env->hstatus, HSTATUS_SPVP); - } else if (mode == PRV_M && access_type != MMU_INST_FETCH) { - if (get_field(env->mstatus, MSTATUS_MPRV)) { - mode = get_field(env->mstatus, MSTATUS_MPP); - } } if (first_stage == false) { diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 0b61f33..4aa1cb4 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -37,6 +37,15 @@ #define MMUIdx_M 3 #define MMU_2STAGE_BIT (1 << 2) +static inline int mmuidx_priv(int mmu_idx) +{ + int ret = mmu_idx & 3; + if (ret == MMUIdx_S_SUM) { + ret = PRV_S; + } + return ret; +} + static inline bool mmuidx_sum(int mmu_idx) { return (mmu_idx & 3) == MMUIdx_S_SUM; |