diff options
| -rw-r--r-- | hw/ide.c | 51 | ||||
| -rw-r--r-- | hw/piix_pci.c | 27 |
2 files changed, 76 insertions, 2 deletions
@@ -2577,6 +2577,55 @@ static int pci_ide_load(QEMUFile* f, void *opaque, int version_id) return 0; } +static void piix3_reset(PCIIDEState *d) +{ + uint8_t *pci_conf = d->dev.config; + + pci_conf[0x04] = 0x00; + pci_conf[0x05] = 0x00; + pci_conf[0x06] = 0x80; /* FBC */ + pci_conf[0x07] = 0x02; // PCI_status_devsel_medium + pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */ +} + +void pci_piix_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn) +{ + PCIIDEState *d; + uint8_t *pci_conf; + + /* register a function 1 of PIIX */ + d = (PCIIDEState *)pci_register_device(bus, "PIIX IDE", + sizeof(PCIIDEState), + devfn, + NULL, NULL); + d->type = IDE_TYPE_PIIX3; + + pci_conf = d->dev.config; + pci_conf[0x00] = 0x86; // Intel + pci_conf[0x01] = 0x80; + pci_conf[0x02] = 0x30; + pci_conf[0x03] = 0x12; + pci_conf[0x08] = 0x02; // Step A1 + pci_conf[0x09] = 0x80; // legacy ATA mode + pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE + pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage + pci_conf[0x0e] = 0x00; // header_type + + piix3_reset(d); + + pci_register_io_region((PCIDevice *)d, 4, 0x10, + PCI_ADDRESS_SPACE_IO, bmdma_map); + + ide_init2(&d->ide_if[0], hd_table[0], hd_table[1], + pic_set_irq_new, isa_pic, 14); + ide_init2(&d->ide_if[2], hd_table[2], hd_table[3], + pic_set_irq_new, isa_pic, 15); + ide_init_ioport(&d->ide_if[0], 0x1f0, 0x3f6); + ide_init_ioport(&d->ide_if[2], 0x170, 0x376); + + register_savevm("ide", 0, 1, pci_ide_save, pci_ide_load, d); +} + /* hd_table must contain 4 block drivers */ /* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */ void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn) @@ -2601,6 +2650,8 @@ void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn) pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage pci_conf[0x0e] = 0x00; // header_type + piix3_reset(d); + pci_register_io_region((PCIDevice *)d, 4, 0x10, PCI_ADDRESS_SPACE_IO, bmdma_map); diff --git a/hw/piix_pci.c b/hw/piix_pci.c index b2b7bf0..1b16652 100644 --- a/hw/piix_pci.c +++ b/hw/piix_pci.c @@ -246,7 +246,6 @@ static void piix3_reset(PCIDevice *d) pci_conf[0x80] = 0x00; pci_conf[0x82] = 0x00; pci_conf[0xa0] = 0x08; - pci_conf[0xa0] = 0x08; pci_conf[0xa2] = 0x00; pci_conf[0xa3] = 0x00; pci_conf[0xa4] = 0x00; @@ -284,7 +283,6 @@ static void piix4_reset(PCIDevice *d) pci_conf[0x80] = 0x00; pci_conf[0x82] = 0x00; pci_conf[0xa0] = 0x08; - pci_conf[0xa0] = 0x08; pci_conf[0xa2] = 0x00; pci_conf[0xa3] = 0x00; pci_conf[0xa4] = 0x00; @@ -312,6 +310,31 @@ static int piix_load(QEMUFile* f, void *opaque, int version_id) return pci_device_load(d, f); } +int piix_init(PCIBus *bus, int devfn) +{ + PCIDevice *d; + uint8_t *pci_conf; + + d = pci_register_device(bus, "PIIX", sizeof(PCIDevice), + devfn, NULL, NULL); + register_savevm("PIIX", 0, 2, piix_save, piix_load, d); + + piix3_dev = d; + pci_conf = d->config; + + pci_conf[0x00] = 0x86; // Intel + pci_conf[0x01] = 0x80; + pci_conf[0x02] = 0x2E; // 82371FB PIIX PCI-to-ISA bridge + pci_conf[0x03] = 0x12; + pci_conf[0x08] = 0x02; // Step A1 + pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA + pci_conf[0x0b] = 0x06; // class_base = PCI_bridge + pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic + + piix3_reset(d); + return d->devfn; +} + int piix3_init(PCIBus *bus, int devfn) { PCIDevice *d; |