diff options
| -rw-r--r-- | Makefile.target | 7 | ||||
| -rw-r--r-- | hw/ide/cmd646.c | 280 | ||||
| -rw-r--r-- | hw/ide/pci.c | 338 | ||||
| -rw-r--r-- | hw/ide/piix.c | 198 |
4 files changed, 482 insertions, 341 deletions
diff --git a/Makefile.target b/Makefile.target index 94bc03b..8d146c5 100644 --- a/Makefile.target +++ b/Makefile.target @@ -188,7 +188,7 @@ obj-y += rtl8139.o obj-y += e1000.o # Hardware support -obj-i386-y = ide/core.o ide/qdev.o ide/isa.o ide/pci.o +obj-i386-y = ide/core.o ide/qdev.o ide/isa.o ide/pci.o ide/piix.o obj-i386-y += pckbd.o $(sound-obj-y) dma.o obj-i386-y += vga.o vga-pci.o vga-isa.o obj-i386-y += fdc.o mc146818rtc.o serial.o i8259.o i8254.o pcspk.o pc.o @@ -199,6 +199,7 @@ obj-i386-y += ne2000-isa.o # shared objects obj-ppc-y = ppc.o ide/core.o ide/qdev.o ide/isa.o ide/pci.o ide/macio.o +obj-ppc-y += ide/cmd646.o obj-ppc-y += vga.o vga-pci.o $(sound-obj-y) dma.o openpic.o # PREP target obj-ppc-y += pckbd.o serial.o i8259.o i8254.o fdc.o mc146818rtc.o @@ -221,7 +222,7 @@ obj-mips-y = mips_r4k.o mips_jazz.o mips_malta.o mips_mipssim.o obj-mips-y += mips_timer.o mips_int.o dma.o vga.o serial.o i8254.o i8259.o rc4030.o obj-mips-y += vga-pci.o vga-isa.o vga-isa-mm.o obj-mips-y += g364fb.o jazz_led.o dp8393x.o -obj-mips-y += ide/core.o ide/qdev.o ide/isa.o ide/pci.o +obj-mips-y += ide/core.o ide/qdev.o ide/isa.o ide/pci.o ide/piix.o obj-mips-y += gt64xxx.o pckbd.o fdc.o mc146818rtc.o usb-uhci.o acpi.o ds1225y.o obj-mips-y += piix4.o parallel.o cirrus_vga.o pcspk.o $(sound-obj-y) obj-mips-y += mipsnet.o ne2000-isa.o @@ -254,7 +255,7 @@ obj-cris-y += pflash_cfi02.o ifeq ($(TARGET_ARCH), sparc64) obj-sparc-y = sun4u.o pckbd.o apb_pci.o -obj-sparc-y += ide/core.o ide/qdev.o ide/pci.o +obj-sparc-y += ide/core.o ide/qdev.o ide/pci.o ide/cmd646.o obj-sparc-y += vga.o vga-pci.o obj-sparc-y += fdc.o mc146818rtc.o serial.o obj-sparc-y += cirrus_vga.o parallel.o diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c new file mode 100644 index 0000000..8c8daa1 --- /dev/null +++ b/hw/ide/cmd646.c @@ -0,0 +1,280 @@ +/* + * QEMU IDE Emulation: PCI cmd646 support. + * + * Copyright (c) 2003 Fabrice Bellard + * Copyright (c) 2006 Openedhand Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#include <hw/hw.h> +#include <hw/pc.h> +#include <hw/pci.h> +#include <hw/isa.h> +#include "block.h" +#include "block_int.h" +#include "sysemu.h" +#include "dma.h" + +#include <hw/ide/pci.h> + +/* CMD646 specific */ +#define MRDMODE 0x71 +#define MRDMODE_INTR_CH0 0x04 +#define MRDMODE_INTR_CH1 0x08 +#define MRDMODE_BLK_CH0 0x10 +#define MRDMODE_BLK_CH1 0x20 +#define UDIDETCR0 0x73 +#define UDIDETCR1 0x7B + +static void cmd646_update_irq(PCIIDEState *d); + +static void ide_map(PCIDevice *pci_dev, int region_num, + uint32_t addr, uint32_t size, int type) +{ + PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, pci_dev); + IDEBus *bus; + + if (region_num <= 3) { + bus = &d->bus[(region_num >> 1)]; + if (region_num & 1) { + register_ioport_read(addr + 2, 1, 1, ide_status_read, bus); + register_ioport_write(addr + 2, 1, 1, ide_cmd_write, bus); + } else { + register_ioport_write(addr, 8, 1, ide_ioport_write, bus); + register_ioport_read(addr, 8, 1, ide_ioport_read, bus); + + /* data ports */ + register_ioport_write(addr, 2, 2, ide_data_writew, bus); + register_ioport_read(addr, 2, 2, ide_data_readw, bus); + register_ioport_write(addr, 4, 4, ide_data_writel, bus); + register_ioport_read(addr, 4, 4, ide_data_readl, bus); + } + } +} + +static uint32_t bmdma_readb(void *opaque, uint32_t addr) +{ + BMDMAState *bm = opaque; + PCIIDEState *pci_dev; + uint32_t val; + + switch(addr & 3) { + case 0: + val = bm->cmd; + break; + case 1: + pci_dev = bm->pci_dev; + if (pci_dev->type == IDE_TYPE_CMD646) { + val = pci_dev->dev.config[MRDMODE]; + } else { + val = 0xff; + } + break; + case 2: + val = bm->status; + break; + case 3: + pci_dev = bm->pci_dev; + if (pci_dev->type == IDE_TYPE_CMD646) { + if (bm == &pci_dev->bmdma[0]) + val = pci_dev->dev.config[UDIDETCR0]; + else + val = pci_dev->dev.config[UDIDETCR1]; + } else { + val = 0xff; + } + break; + default: + val = 0xff; + break; + } +#ifdef DEBUG_IDE + printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val); +#endif + return val; +} + +static void bmdma_writeb(void *opaque, uint32_t addr, uint32_t val) +{ + BMDMAState *bm = opaque; + PCIIDEState *pci_dev; +#ifdef DEBUG_IDE + printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val); +#endif + switch(addr & 3) { + case 1: + pci_dev = bm->pci_dev; + if (pci_dev->type == IDE_TYPE_CMD646) { + pci_dev->dev.config[MRDMODE] = + (pci_dev->dev.config[MRDMODE] & ~0x30) | (val & 0x30); + cmd646_update_irq(pci_dev); + } + break; + case 2: + bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06); + break; + case 3: + pci_dev = bm->pci_dev; + if (pci_dev->type == IDE_TYPE_CMD646) { + if (bm == &pci_dev->bmdma[0]) + pci_dev->dev.config[UDIDETCR0] = val; + else + pci_dev->dev.config[UDIDETCR1] = val; + } + break; + } +} + +static void bmdma_map(PCIDevice *pci_dev, int region_num, + uint32_t addr, uint32_t size, int type) +{ + PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, pci_dev); + int i; + + for(i = 0;i < 2; i++) { + BMDMAState *bm = &d->bmdma[i]; + d->bus[i].bmdma = bm; + bm->pci_dev = DO_UPCAST(PCIIDEState, dev, pci_dev); + bm->bus = d->bus+i; + qemu_add_vm_change_state_handler(ide_dma_restart_cb, bm); + + register_ioport_write(addr, 1, 1, bmdma_cmd_writeb, bm); + + register_ioport_write(addr + 1, 3, 1, bmdma_writeb, bm); + register_ioport_read(addr, 4, 1, bmdma_readb, bm); + + register_ioport_write(addr + 4, 4, 1, bmdma_addr_writeb, bm); + register_ioport_read(addr + 4, 4, 1, bmdma_addr_readb, bm); + register_ioport_write(addr + 4, 4, 2, bmdma_addr_writew, bm); + register_ioport_read(addr + 4, 4, 2, bmdma_addr_readw, bm); + register_ioport_write(addr + 4, 4, 4, bmdma_addr_writel, bm); + register_ioport_read(addr + 4, 4, 4, bmdma_addr_readl, bm); + addr += 8; + } +} + +/* XXX: call it also when the MRDMODE is changed from the PCI config + registers */ +static void cmd646_update_irq(PCIIDEState *d) +{ + int pci_level; + pci_level = ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH0) && + !(d->dev.config[MRDMODE] & MRDMODE_BLK_CH0)) || + ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH1) && + !(d->dev.config[MRDMODE] & MRDMODE_BLK_CH1)); + qemu_set_irq(d->dev.irq[0], pci_level); +} + +/* the PCI irq level is the logical OR of the two channels */ +static void cmd646_set_irq(void *opaque, int channel, int level) +{ + PCIIDEState *d = opaque; + int irq_mask; + + irq_mask = MRDMODE_INTR_CH0 << channel; + if (level) + d->dev.config[MRDMODE] |= irq_mask; + else + d->dev.config[MRDMODE] &= ~irq_mask; + cmd646_update_irq(d); +} + +static void cmd646_reset(void *opaque) +{ + PCIIDEState *d = opaque; + unsigned int i; + + for (i = 0; i < 2; i++) + ide_dma_cancel(&d->bmdma[i]); +} + +/* CMD646 PCI IDE controller */ +static int pci_cmd646_ide_initfn(PCIDevice *dev) +{ + PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev); + uint8_t *pci_conf = d->dev.config; + qemu_irq *irq; + + d->type = IDE_TYPE_CMD646; + pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_CMD); + pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_CMD_646); + + pci_conf[0x08] = 0x07; // IDE controller revision + pci_conf[0x09] = 0x8f; + + pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE); + pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type + + pci_conf[0x51] = 0x04; // enable IDE0 + if (d->secondary) { + /* XXX: if not enabled, really disable the seconday IDE controller */ + pci_conf[0x51] |= 0x08; /* enable IDE1 */ + } + + pci_register_bar(dev, 0, 0x8, PCI_ADDRESS_SPACE_IO, ide_map); + pci_register_bar(dev, 1, 0x4, PCI_ADDRESS_SPACE_IO, ide_map); + pci_register_bar(dev, 2, 0x8, PCI_ADDRESS_SPACE_IO, ide_map); + pci_register_bar(dev, 3, 0x4, PCI_ADDRESS_SPACE_IO, ide_map); + pci_register_bar(dev, 4, 0x10, PCI_ADDRESS_SPACE_IO, bmdma_map); + + pci_conf[0x3d] = 0x01; // interrupt on pin 1 + + irq = qemu_allocate_irqs(cmd646_set_irq, d, 2); + ide_bus_new(&d->bus[0], &d->dev.qdev); + ide_bus_new(&d->bus[1], &d->dev.qdev); + ide_init2(&d->bus[0], NULL, NULL, irq[0]); + ide_init2(&d->bus[1], NULL, NULL, irq[1]); + + register_savevm("ide", 0, 3, pci_ide_save, pci_ide_load, d); + qemu_register_reset(cmd646_reset, d); + cmd646_reset(d); + return 0; +} + +void pci_cmd646_ide_init(PCIBus *bus, DriveInfo **hd_table, + int secondary_ide_enabled) +{ + PCIDevice *dev; + + dev = pci_create(bus, -1, "CMD646 IDE"); + qdev_prop_set_uint32(&dev->qdev, "secondary", secondary_ide_enabled); + qdev_init_nofail(&dev->qdev); + + pci_ide_create_devs(dev, hd_table); +} + +static PCIDeviceInfo cmd646_ide_info[] = { + { + .qdev.name = "CMD646 IDE", + .qdev.size = sizeof(PCIIDEState), + .init = pci_cmd646_ide_initfn, + .qdev.props = (Property[]) { + DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0), + DEFINE_PROP_END_OF_LIST(), + }, + },{ + /* end of list */ + } +}; + +static void cmd646_ide_register(void) +{ + pci_qdev_register_many(cmd646_ide_info); +} +device_init(cmd646_ide_register); diff --git a/hw/ide/pci.c b/hw/ide/pci.c index af4d7a4..dea126a 100644 --- a/hw/ide/pci.c +++ b/hw/ide/pci.c @@ -33,44 +33,6 @@ #include <hw/ide/pci.h> -/***********************************************************/ -/* PCI IDE definitions */ - -/* CMD646 specific */ -#define MRDMODE 0x71 -#define MRDMODE_INTR_CH0 0x04 -#define MRDMODE_INTR_CH1 0x08 -#define MRDMODE_BLK_CH0 0x10 -#define MRDMODE_BLK_CH1 0x20 -#define UDIDETCR0 0x73 -#define UDIDETCR1 0x7B - -static void cmd646_update_irq(PCIIDEState *d); - -static void ide_map(PCIDevice *pci_dev, int region_num, - uint32_t addr, uint32_t size, int type) -{ - PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, pci_dev); - IDEBus *bus; - - if (region_num <= 3) { - bus = &d->bus[(region_num >> 1)]; - if (region_num & 1) { - register_ioport_read(addr + 2, 1, 1, ide_status_read, bus); - register_ioport_write(addr + 2, 1, 1, ide_cmd_write, bus); - } else { - register_ioport_write(addr, 8, 1, ide_ioport_write, bus); - register_ioport_read(addr, 8, 1, ide_ioport_read, bus); - - /* data ports */ - register_ioport_write(addr, 2, 2, ide_data_writew, bus); - register_ioport_read(addr, 2, 2, ide_data_readw, bus); - register_ioport_write(addr, 4, 4, ide_data_writel, bus); - register_ioport_read(addr, 4, 4, ide_data_readl, bus); - } - } -} - void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val) { BMDMAState *bm = opaque; @@ -92,79 +54,6 @@ void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val) } } -static uint32_t bmdma_readb(void *opaque, uint32_t addr) -{ - BMDMAState *bm = opaque; - PCIIDEState *pci_dev; - uint32_t val; - - switch(addr & 3) { - case 0: - val = bm->cmd; - break; - case 1: - pci_dev = bm->pci_dev; - if (pci_dev->type == IDE_TYPE_CMD646) { - val = pci_dev->dev.config[MRDMODE]; - } else { - val = 0xff; - } - break; - case 2: - val = bm->status; - break; - case 3: - pci_dev = bm->pci_dev; - if (pci_dev->type == IDE_TYPE_CMD646) { - if (bm == &pci_dev->bmdma[0]) - val = pci_dev->dev.config[UDIDETCR0]; - else - val = pci_dev->dev.config[UDIDETCR1]; - } else { - val = 0xff; - } - break; - default: - val = 0xff; - break; - } -#ifdef DEBUG_IDE - printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val); -#endif - return val; -} - -static void bmdma_writeb(void *opaque, uint32_t addr, uint32_t val) -{ - BMDMAState *bm = opaque; - PCIIDEState *pci_dev; -#ifdef DEBUG_IDE - printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val); -#endif - switch(addr & 3) { - case 1: - pci_dev = bm->pci_dev; - if (pci_dev->type == IDE_TYPE_CMD646) { - pci_dev->dev.config[MRDMODE] = - (pci_dev->dev.config[MRDMODE] & ~0x30) | (val & 0x30); - cmd646_update_irq(pci_dev); - } - break; - case 2: - bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06); - break; - case 3: - pci_dev = bm->pci_dev; - if (pci_dev->type == IDE_TYPE_CMD646) { - if (bm == &pci_dev->bmdma[0]) - pci_dev->dev.config[UDIDETCR0] = val; - else - pci_dev->dev.config[UDIDETCR1] = val; - } - break; - } -} - uint32_t bmdma_addr_readb(void *opaque, uint32_t addr) { BMDMAState *bm = opaque; @@ -232,34 +121,6 @@ void bmdma_addr_writel(void *opaque, uint32_t addr, uint32_t val) bm->cur_addr = bm->addr; } -static void bmdma_map(PCIDevice *pci_dev, int region_num, - uint32_t addr, uint32_t size, int type) -{ - PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, pci_dev); - int i; - - for(i = 0;i < 2; i++) { - BMDMAState *bm = &d->bmdma[i]; - d->bus[i].bmdma = bm; - bm->pci_dev = DO_UPCAST(PCIIDEState, dev, pci_dev); - bm->bus = d->bus+i; - qemu_add_vm_change_state_handler(ide_dma_restart_cb, bm); - - register_ioport_write(addr, 1, 1, bmdma_cmd_writeb, bm); - - register_ioport_write(addr + 1, 3, 1, bmdma_writeb, bm); - register_ioport_read(addr, 4, 1, bmdma_readb, bm); - - register_ioport_write(addr + 4, 4, 1, bmdma_addr_writeb, bm); - register_ioport_read(addr + 4, 4, 1, bmdma_addr_readb, bm); - register_ioport_write(addr + 4, 4, 2, bmdma_addr_writew, bm); - register_ioport_read(addr + 4, 4, 2, bmdma_addr_readw, bm); - register_ioport_write(addr + 4, 4, 4, bmdma_addr_writel, bm); - register_ioport_read(addr + 4, 4, 4, bmdma_addr_readl, bm); - addr += 8; - } -} - void pci_ide_save(QEMUFile* f, void *opaque) { PCIIDEState *d = opaque; @@ -342,202 +203,3 @@ void pci_ide_create_devs(PCIDevice *dev, DriveInfo **hd_table) ide_create_drive(d->bus+bus[i], unit[i], hd_table[i]); } } - -/* XXX: call it also when the MRDMODE is changed from the PCI config - registers */ -static void cmd646_update_irq(PCIIDEState *d) -{ - int pci_level; - pci_level = ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH0) && - !(d->dev.config[MRDMODE] & MRDMODE_BLK_CH0)) || - ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH1) && - !(d->dev.config[MRDMODE] & MRDMODE_BLK_CH1)); - qemu_set_irq(d->dev.irq[0], pci_level); -} - -/* the PCI irq level is the logical OR of the two channels */ -static void cmd646_set_irq(void *opaque, int channel, int level) -{ - PCIIDEState *d = opaque; - int irq_mask; - - irq_mask = MRDMODE_INTR_CH0 << channel; - if (level) - d->dev.config[MRDMODE] |= irq_mask; - else - d->dev.config[MRDMODE] &= ~irq_mask; - cmd646_update_irq(d); -} - -static void cmd646_reset(void *opaque) -{ - PCIIDEState *d = opaque; - unsigned int i; - - for (i = 0; i < 2; i++) - ide_dma_cancel(&d->bmdma[i]); -} - -/* CMD646 PCI IDE controller */ -static int pci_cmd646_ide_initfn(PCIDevice *dev) -{ - PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev); - uint8_t *pci_conf = d->dev.config; - qemu_irq *irq; - - d->type = IDE_TYPE_CMD646; - pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_CMD); - pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_CMD_646); - - pci_conf[0x08] = 0x07; // IDE controller revision - pci_conf[0x09] = 0x8f; - - pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE); - pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type - - pci_conf[0x51] = 0x04; // enable IDE0 - if (d->secondary) { - /* XXX: if not enabled, really disable the seconday IDE controller */ - pci_conf[0x51] |= 0x08; /* enable IDE1 */ - } - - pci_register_bar(dev, 0, 0x8, PCI_ADDRESS_SPACE_IO, ide_map); - pci_register_bar(dev, 1, 0x4, PCI_ADDRESS_SPACE_IO, ide_map); - pci_register_bar(dev, 2, 0x8, PCI_ADDRESS_SPACE_IO, ide_map); - pci_register_bar(dev, 3, 0x4, PCI_ADDRESS_SPACE_IO, ide_map); - pci_register_bar(dev, 4, 0x10, PCI_ADDRESS_SPACE_IO, bmdma_map); - - pci_conf[0x3d] = 0x01; // interrupt on pin 1 - - irq = qemu_allocate_irqs(cmd646_set_irq, d, 2); - ide_bus_new(&d->bus[0], &d->dev.qdev); - ide_bus_new(&d->bus[1], &d->dev.qdev); - ide_init2(&d->bus[0], NULL, NULL, irq[0]); - ide_init2(&d->bus[1], NULL, NULL, irq[1]); - - register_savevm("ide", 0, 3, pci_ide_save, pci_ide_load, d); - qemu_register_reset(cmd646_reset, d); - cmd646_reset(d); - return 0; -} - -void pci_cmd646_ide_init(PCIBus *bus, DriveInfo **hd_table, - int secondary_ide_enabled) -{ - PCIDevice *dev; - - dev = pci_create(bus, -1, "CMD646 IDE"); - qdev_prop_set_uint32(&dev->qdev, "secondary", secondary_ide_enabled); - qdev_init_nofail(&dev->qdev); - - pci_ide_create_devs(dev, hd_table); -} - -static void piix3_reset(void *opaque) -{ - PCIIDEState *d = opaque; - uint8_t *pci_conf = d->dev.config; - int i; - - for (i = 0; i < 2; i++) - ide_dma_cancel(&d->bmdma[i]); - - pci_conf[0x04] = 0x00; - pci_conf[0x05] = 0x00; - pci_conf[0x06] = 0x80; /* FBC */ - pci_conf[0x07] = 0x02; // PCI_status_devsel_medium - pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */ -} - -static int pci_piix_ide_initfn(PCIIDEState *d) -{ - uint8_t *pci_conf = d->dev.config; - - pci_conf[0x09] = 0x80; // legacy ATA mode - pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE); - pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type - - qemu_register_reset(piix3_reset, d); - piix3_reset(d); - - pci_register_bar(&d->dev, 4, 0x10, PCI_ADDRESS_SPACE_IO, bmdma_map); - - register_savevm("ide", 0, 3, pci_ide_save, pci_ide_load, d); - - ide_bus_new(&d->bus[0], &d->dev.qdev); - ide_bus_new(&d->bus[1], &d->dev.qdev); - ide_init_ioport(&d->bus[0], 0x1f0, 0x3f6); - ide_init_ioport(&d->bus[1], 0x170, 0x376); - - ide_init2(&d->bus[0], NULL, NULL, isa_reserve_irq(14)); - ide_init2(&d->bus[1], NULL, NULL, isa_reserve_irq(15)); - return 0; -} - -static int pci_piix3_ide_initfn(PCIDevice *dev) -{ - PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev); - - d->type = IDE_TYPE_PIIX3; - pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL); - pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82371SB_1); - return pci_piix_ide_initfn(d); -} - -static int pci_piix4_ide_initfn(PCIDevice *dev) -{ - PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev); - - d->type = IDE_TYPE_PIIX4; - pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL); - pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82371AB); - return pci_piix_ide_initfn(d); -} - -/* hd_table must contain 4 block drivers */ -/* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */ -void pci_piix3_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn) -{ - PCIDevice *dev; - - dev = pci_create_simple(bus, devfn, "PIIX3 IDE"); - pci_ide_create_devs(dev, hd_table); -} - -/* hd_table must contain 4 block drivers */ -/* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */ -void pci_piix4_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn) -{ - PCIDevice *dev; - - dev = pci_create_simple(bus, devfn, "PIIX4 IDE"); - pci_ide_create_devs(dev, hd_table); -} - -static PCIDeviceInfo piix_ide_info[] = { - { - .qdev.name = "PIIX3 IDE", - .qdev.size = sizeof(PCIIDEState), - .init = pci_piix3_ide_initfn, - },{ - .qdev.name = "PIIX4 IDE", - .qdev.size = sizeof(PCIIDEState), - .init = pci_piix4_ide_initfn, - },{ - .qdev.name = "CMD646 IDE", - .qdev.size = sizeof(PCIIDEState), - .init = pci_cmd646_ide_initfn, - .qdev.props = (Property[]) { - DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0), - DEFINE_PROP_END_OF_LIST(), - }, - },{ - /* end of list */ - } -}; - -static void piix_ide_register(void) -{ - pci_qdev_register_many(piix_ide_info); -} -device_init(piix_ide_register); diff --git a/hw/ide/piix.c b/hw/ide/piix.c new file mode 100644 index 0000000..47d736d --- /dev/null +++ b/hw/ide/piix.c @@ -0,0 +1,198 @@ +/* + * QEMU IDE Emulation: PCI PIIX3/4 support. + * + * Copyright (c) 2003 Fabrice Bellard + * Copyright (c) 2006 Openedhand Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#include <hw/hw.h> +#include <hw/pc.h> +#include <hw/pci.h> +#include <hw/isa.h> +#include "block.h" +#include "block_int.h" +#include "sysemu.h" +#include "dma.h" + +#include <hw/ide/pci.h> + +static uint32_t bmdma_readb(void *opaque, uint32_t addr) +{ + BMDMAState *bm = opaque; + uint32_t val; + + switch(addr & 3) { + case 0: + val = bm->cmd; + break; + case 2: + val = bm->status; + break; + default: + val = 0xff; + break; + } +#ifdef DEBUG_IDE + printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val); +#endif + return val; +} + +static void bmdma_writeb(void *opaque, uint32_t addr, uint32_t val) +{ + BMDMAState *bm = opaque; +#ifdef DEBUG_IDE + printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val); +#endif + switch(addr & 3) { + case 2: + bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06); + break; + } +} + +static void bmdma_map(PCIDevice *pci_dev, int region_num, + uint32_t addr, uint32_t size, int type) +{ + PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, pci_dev); + int i; + + for(i = 0;i < 2; i++) { + BMDMAState *bm = &d->bmdma[i]; + d->bus[i].bmdma = bm; + bm->pci_dev = DO_UPCAST(PCIIDEState, dev, pci_dev); + bm->bus = d->bus+i; + qemu_add_vm_change_state_handler(ide_dma_restart_cb, bm); + + register_ioport_write(addr, 1, 1, bmdma_cmd_writeb, bm); + + register_ioport_write(addr + 1, 3, 1, bmdma_writeb, bm); + register_ioport_read(addr, 4, 1, bmdma_readb, bm); + + register_ioport_write(addr + 4, 4, 1, bmdma_addr_writeb, bm); + register_ioport_read(addr + 4, 4, 1, bmdma_addr_readb, bm); + register_ioport_write(addr + 4, 4, 2, bmdma_addr_writew, bm); + register_ioport_read(addr + 4, 4, 2, bmdma_addr_readw, bm); + register_ioport_write(addr + 4, 4, 4, bmdma_addr_writel, bm); + register_ioport_read(addr + 4, 4, 4, bmdma_addr_readl, bm); + addr += 8; + } +} + +static void piix3_reset(void *opaque) +{ + PCIIDEState *d = opaque; + uint8_t *pci_conf = d->dev.config; + int i; + + for (i = 0; i < 2; i++) + ide_dma_cancel(&d->bmdma[i]); + + pci_conf[0x04] = 0x00; + pci_conf[0x05] = 0x00; + pci_conf[0x06] = 0x80; /* FBC */ + pci_conf[0x07] = 0x02; // PCI_status_devsel_medium + pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */ +} + +static int pci_piix_ide_initfn(PCIIDEState *d) +{ + uint8_t *pci_conf = d->dev.config; + + pci_conf[0x09] = 0x80; // legacy ATA mode + pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE); + pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type + + qemu_register_reset(piix3_reset, d); + piix3_reset(d); + + pci_register_bar(&d->dev, 4, 0x10, PCI_ADDRESS_SPACE_IO, bmdma_map); + + register_savevm("ide", 0, 3, pci_ide_save, pci_ide_load, d); + + ide_bus_new(&d->bus[0], &d->dev.qdev); + ide_bus_new(&d->bus[1], &d->dev.qdev); + ide_init_ioport(&d->bus[0], 0x1f0, 0x3f6); + ide_init_ioport(&d->bus[1], 0x170, 0x376); + + ide_init2(&d->bus[0], NULL, NULL, isa_reserve_irq(14)); + ide_init2(&d->bus[1], NULL, NULL, isa_reserve_irq(15)); + return 0; +} + +static int pci_piix3_ide_initfn(PCIDevice *dev) +{ + PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev); + + d->type = IDE_TYPE_PIIX3; + pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL); + pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82371SB_1); + return pci_piix_ide_initfn(d); +} + +static int pci_piix4_ide_initfn(PCIDevice *dev) +{ + PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev); + + d->type = IDE_TYPE_PIIX4; + pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL); + pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82371AB); + return pci_piix_ide_initfn(d); +} + +/* hd_table must contain 4 block drivers */ +/* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */ +void pci_piix3_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn) +{ + PCIDevice *dev; + + dev = pci_create_simple(bus, devfn, "PIIX3 IDE"); + pci_ide_create_devs(dev, hd_table); +} + +/* hd_table must contain 4 block drivers */ +/* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */ +void pci_piix4_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn) +{ + PCIDevice *dev; + + dev = pci_create_simple(bus, devfn, "PIIX4 IDE"); + pci_ide_create_devs(dev, hd_table); +} + +static PCIDeviceInfo piix_ide_info[] = { + { + .qdev.name = "PIIX3 IDE", + .qdev.size = sizeof(PCIIDEState), + .init = pci_piix3_ide_initfn, + },{ + .qdev.name = "PIIX4 IDE", + .qdev.size = sizeof(PCIIDEState), + .init = pci_piix4_ide_initfn, + },{ + /* end of list */ + } +}; + +static void piix_ide_register(void) +{ + pci_qdev_register_many(piix_ide_info); +} +device_init(piix_ide_register); |