diff options
-rw-r--r-- | target-alpha/translate.c | 3 | ||||
-rw-r--r-- | target-arm/translate-a64.c | 3 | ||||
-rw-r--r-- | target-arm/translate.c | 6 | ||||
-rw-r--r-- | target-cris/translate.c | 3 | ||||
-rw-r--r-- | target-i386/translate.c | 6 | ||||
-rw-r--r-- | target-lm32/translate.c | 3 | ||||
-rw-r--r-- | target-m68k/translate.c | 6 | ||||
-rw-r--r-- | target-microblaze/translate.c | 6 | ||||
-rw-r--r-- | target-mips/translate.c | 7 | ||||
-rw-r--r-- | target-moxie/translate.c | 13 | ||||
-rw-r--r-- | target-openrisc/translate.c | 3 | ||||
-rw-r--r-- | target-ppc/translate.c | 6 | ||||
-rw-r--r-- | target-s390x/translate.c | 3 | ||||
-rw-r--r-- | target-sh4/translate.c | 7 | ||||
-rw-r--r-- | target-sparc/translate.c | 7 | ||||
-rw-r--r-- | target-tilegx/translate.c | 3 | ||||
-rw-r--r-- | target-tricore/translate.c | 20 | ||||
-rw-r--r-- | target-unicore32/translate.c | 3 | ||||
-rw-r--r-- | target-xtensa/translate.c | 3 | ||||
-rw-r--r-- | tcg/tcg.h | 1 |
20 files changed, 95 insertions, 17 deletions
diff --git a/target-alpha/translate.c b/target-alpha/translate.c index c10193e..538e202 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -2903,6 +2903,9 @@ static inline void gen_intermediate_code_internal(AlphaCPU *cpu, if (max_insns == 0) { max_insns = CF_COUNT_MASK; } + if (max_insns > TCG_MAX_INSNS) { + max_insns = TCG_MAX_INSNS; + } if (in_superpage(&ctx, pc_start)) { pc_mask = (1ULL << 41) - 1; diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 654a586..5022fc3 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -11072,6 +11072,9 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, if (max_insns == 0) { max_insns = CF_COUNT_MASK; } + if (max_insns > TCG_MAX_INSNS) { + max_insns = TCG_MAX_INSNS; + } gen_tb_start(tb); diff --git a/target-arm/translate.c b/target-arm/translate.c index fb69ecb..fedb781 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -11258,8 +11258,12 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, lj = -1; num_insns = 0; max_insns = tb->cflags & CF_COUNT_MASK; - if (max_insns == 0) + if (max_insns == 0) { max_insns = CF_COUNT_MASK; + } + if (max_insns > TCG_MAX_INSNS) { + max_insns = TCG_MAX_INSNS; + } gen_tb_start(tb); diff --git a/target-cris/translate.c b/target-cris/translate.c index 3d55a6a..d038bdb 100644 --- a/target-cris/translate.c +++ b/target-cris/translate.c @@ -3155,6 +3155,9 @@ gen_intermediate_code_internal(CRISCPU *cpu, TranslationBlock *tb, if (max_insns == 0) { max_insns = CF_COUNT_MASK; } + if (max_insns > TCG_MAX_INSNS) { + max_insns = TCG_MAX_INSNS; + } gen_tb_start(tb); do { diff --git a/target-i386/translate.c b/target-i386/translate.c index 7501b91..d3282e8 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -7932,8 +7932,12 @@ static inline void gen_intermediate_code_internal(X86CPU *cpu, lj = -1; num_insns = 0; max_insns = tb->cflags & CF_COUNT_MASK; - if (max_insns == 0) + if (max_insns == 0) { max_insns = CF_COUNT_MASK; + } + if (max_insns > TCG_MAX_INSNS) { + max_insns = TCG_MAX_INSNS; + } gen_tb_start(tb); for(;;) { diff --git a/target-lm32/translate.c b/target-lm32/translate.c index 8ea7929..e16c31a 100644 --- a/target-lm32/translate.c +++ b/target-lm32/translate.c @@ -1069,6 +1069,9 @@ void gen_intermediate_code_internal(LM32CPU *cpu, if (max_insns == 0) { max_insns = CF_COUNT_MASK; } + if (max_insns > TCG_MAX_INSNS) { + max_insns = TCG_MAX_INSNS; + } gen_tb_start(tb); do { diff --git a/target-m68k/translate.c b/target-m68k/translate.c index afef37f..185c565 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -2991,8 +2991,12 @@ gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb, lj = -1; num_insns = 0; max_insns = tb->cflags & CF_COUNT_MASK; - if (max_insns == 0) + if (max_insns == 0) { max_insns = CF_COUNT_MASK; + } + if (max_insns > TCG_MAX_INSNS) { + max_insns = TCG_MAX_INSNS; + } gen_tb_start(tb); do { diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index 1224456..58b27ca 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -1674,8 +1674,12 @@ gen_intermediate_code_internal(MicroBlazeCPU *cpu, TranslationBlock *tb, lj = -1; num_insns = 0; max_insns = tb->cflags & CF_COUNT_MASK; - if (max_insns == 0) + if (max_insns == 0) { max_insns = CF_COUNT_MASK; + } + if (max_insns > TCG_MAX_INSNS) { + max_insns = TCG_MAX_INSNS; + } gen_tb_start(tb); do diff --git a/target-mips/translate.c b/target-mips/translate.c index 30d7d46..c0a0674 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -19586,8 +19586,13 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb, MO_UNALN : MO_ALIGN; num_insns = 0; max_insns = tb->cflags & CF_COUNT_MASK; - if (max_insns == 0) + if (max_insns == 0) { max_insns = CF_COUNT_MASK; + } + if (max_insns > TCG_MAX_INSNS) { + max_insns = TCG_MAX_INSNS; + } + LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx.mem_idx, ctx.hflags); gen_tb_start(tb); while (ctx.bstate == BS_NONE) { diff --git a/target-moxie/translate.c b/target-moxie/translate.c index d71f55b..68588da 100644 --- a/target-moxie/translate.c +++ b/target-moxie/translate.c @@ -824,7 +824,7 @@ gen_intermediate_code_internal(MoxieCPU *cpu, TranslationBlock *tb, target_ulong pc_start; int j, lj = -1; CPUMoxieState *env = &cpu->env; - int num_insns; + int num_insns, max_insns; pc_start = tb->pc; ctx.pc = pc_start; @@ -834,6 +834,13 @@ gen_intermediate_code_internal(MoxieCPU *cpu, TranslationBlock *tb, ctx.singlestep_enabled = 0; ctx.bstate = BS_NONE; num_insns = 0; + max_insns = tb->cflags & CF_COUNT_MASK; + if (max_insns == 0) { + max_insns = CF_COUNT_MASK; + } + if (max_insns > TCG_MAX_INSNS) { + max_insns = TCG_MAX_INSNS; + } gen_tb_start(tb); do { @@ -862,10 +869,12 @@ gen_intermediate_code_internal(MoxieCPU *cpu, TranslationBlock *tb, ctx.opcode = cpu_lduw_code(env, ctx.pc); ctx.pc += decode_opc(cpu, &ctx); + if (num_insns >= max_insns) { + break; + } if (cs->singlestep_enabled) { break; } - if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) { break; } diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c index 9755850..7573d34 100644 --- a/target-openrisc/translate.c +++ b/target-openrisc/translate.c @@ -1654,6 +1654,9 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu, if (max_insns == 0) { max_insns = CF_COUNT_MASK; } + if (max_insns > TCG_MAX_INSNS) { + max_insns = TCG_MAX_INSNS; + } gen_tb_start(tb); diff --git a/target-ppc/translate.c b/target-ppc/translate.c index fc234a3..2dc6fb4 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -11475,8 +11475,12 @@ static inline void gen_intermediate_code_internal(PowerPCCPU *cpu, #endif num_insns = 0; max_insns = tb->cflags & CF_COUNT_MASK; - if (max_insns == 0) + if (max_insns == 0) { max_insns = CF_COUNT_MASK; + } + if (max_insns > TCG_MAX_INSNS) { + max_insns = TCG_MAX_INSNS; + } gen_tb_start(tb); tcg_clear_temp_count(); diff --git a/target-s390x/translate.c b/target-s390x/translate.c index 6bbc760..b1aa139 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -5352,6 +5352,9 @@ static inline void gen_intermediate_code_internal(S390CPU *cpu, if (max_insns == 0) { max_insns = CF_COUNT_MASK; } + if (max_insns > TCG_MAX_INSNS) { + max_insns = TCG_MAX_INSNS; + } gen_tb_start(tb); diff --git a/target-sh4/translate.c b/target-sh4/translate.c index efaa6f6..b48b9bb 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -1844,8 +1844,13 @@ gen_intermediate_code_internal(SuperHCPU *cpu, TranslationBlock *tb, ii = -1; num_insns = 0; max_insns = tb->cflags & CF_COUNT_MASK; - if (max_insns == 0) + if (max_insns == 0) { max_insns = CF_COUNT_MASK; + } + if (max_insns > TCG_MAX_INSNS) { + max_insns = TCG_MAX_INSNS; + } + gen_tb_start(tb); while (ctx.bstate == BS_NONE && !tcg_op_buf_full()) { if (search_pc) { diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 6e5b82d..e6ecd21 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -5236,8 +5236,13 @@ static inline void gen_intermediate_code_internal(SPARCCPU *cpu, num_insns = 0; max_insns = tb->cflags & CF_COUNT_MASK; - if (max_insns == 0) + if (max_insns == 0) { max_insns = CF_COUNT_MASK; + } + if (max_insns > TCG_MAX_INSNS) { + max_insns = TCG_MAX_INSNS; + } + gen_tb_start(tb); do { if (spc) { diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c index c23b761..a6b9cd8 100644 --- a/target-tilegx/translate.c +++ b/target-tilegx/translate.c @@ -2081,6 +2081,9 @@ static inline void gen_intermediate_code_internal(TileGXCPU *cpu, if (cs->singlestep_enabled || singlestep) { max_insns = 1; } + if (max_insns > TCG_MAX_INSNS) { + max_insns = TCG_MAX_INSNS; + } gen_tb_start(tb); while (1) { diff --git a/target-tricore/translate.c b/target-tricore/translate.c index fa10d5c..5345486 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -8274,13 +8274,24 @@ gen_intermediate_code_internal(TriCoreCPU *cpu, struct TranslationBlock *tb, CPUTriCoreState *env = &cpu->env; DisasContext ctx; target_ulong pc_start; - int num_insns; + int num_insns, max_insns; if (search_pc) { qemu_log("search pc %d\n", search_pc); } num_insns = 0; + max_insns = tb->cflags & CF_COUNT_MASK; + if (max_insns == 0) { + max_insns = CF_COUNT_MASK; + } + if (singlestep) { + max_insns = 1; + } + if (max_insns > TCG_MAX_INSNS) { + max_insns = TCG_MAX_INSNS; + } + pc_start = tb->pc; ctx.pc = pc_start; ctx.saved_pc = -1; @@ -8298,12 +8309,7 @@ gen_intermediate_code_internal(TriCoreCPU *cpu, struct TranslationBlock *tb, ctx.opcode = cpu_ldl_code(env, ctx.pc); decode_opc(env, &ctx, 0); - if (tcg_op_buf_full()) { - gen_save_pc(ctx.next_pc); - tcg_gen_exit_tb(0); - break; - } - if (singlestep) { + if (num_insns >= max_insns || tcg_op_buf_full()) { gen_save_pc(ctx.next_pc); tcg_gen_exit_tb(0); break; diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c index cd23c4b..5e61e38 100644 --- a/target-unicore32/translate.c +++ b/target-unicore32/translate.c @@ -1900,6 +1900,9 @@ static inline void gen_intermediate_code_internal(UniCore32CPU *cpu, if (max_insns == 0) { max_insns = CF_COUNT_MASK; } + if (max_insns > TCG_MAX_INSNS) { + max_insns = TCG_MAX_INSNS; + } #ifndef CONFIG_USER_ONLY if ((env->uncached_asr & ASR_M) == ASR_MODE_USER) { diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index ea87cb5..4d4dc06 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -3014,6 +3014,9 @@ void gen_intermediate_code_internal(XtensaCPU *cpu, if (max_insns == 0) { max_insns = CF_COUNT_MASK; } + if (max_insns > TCG_MAX_INSNS) { + max_insns = TCG_MAX_INSNS; + } dc.config = env->config; dc.singlestep_enabled = cs->singlestep_enabled; @@ -194,6 +194,7 @@ typedef struct TCGPool { #define TCG_POOL_CHUNK_SIZE 32768 #define TCG_MAX_TEMPS 512 +#define TCG_MAX_INSNS 512 /* when the size of the arguments of a called function is smaller than this value, they are statically allocated in the TB stack frame */ |