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-rwxr-xr-xconfigure3
-rw-r--r--cpu-defs.h17
-rw-r--r--exec.c2
-rw-r--r--softmmu_template.h28
-rw-r--r--targphys.h5
-rw-r--r--tcg/mips/tcg-target.c4
-rw-r--r--tcg/ppc/tcg-target.c12
-rw-r--r--tcg/ppc64/tcg-target.c12
-rw-r--r--tcg/sparc/tcg-target.c8
9 files changed, 32 insertions, 59 deletions
diff --git a/configure b/configure
index 73d566f..1d5fb17 100755
--- a/configure
+++ b/configure
@@ -2538,9 +2538,6 @@ if [ "$TARGET_ABI_DIR" = "" ]; then
TARGET_ABI_DIR=$TARGET_ARCH
fi
echo "TARGET_ABI_DIR=$TARGET_ABI_DIR" >> $config_target_mak
-if [ $target_phys_bits -lt $hostlongbits ] ; then
- target_phys_bits=$hostlongbits
-fi
case "$target_arch2" in
i386|x86_64)
if test "$xen" = "yes" -a "$target_softmmu" = "yes" ; then
diff --git a/cpu-defs.h b/cpu-defs.h
index 2e94585..0140596 100644
--- a/cpu-defs.h
+++ b/cpu-defs.h
@@ -76,7 +76,7 @@ typedef uint64_t target_ulong;
#define CPU_TLB_BITS 8
#define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
-#if TARGET_PHYS_ADDR_BITS == 32 && TARGET_LONG_BITS == 32
+#if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32
#define CPU_TLB_ENTRY_BITS 4
#else
#define CPU_TLB_ENTRY_BITS 5
@@ -92,21 +92,18 @@ typedef struct CPUTLBEntry {
target_ulong addr_read;
target_ulong addr_write;
target_ulong addr_code;
- /* Addend to virtual address to get physical address. IO accesses
+ /* Addend to virtual address to get host address. IO accesses
use the corresponding iotlb value. */
-#if TARGET_PHYS_ADDR_BITS == 64
- /* on i386 Linux make sure it is aligned */
- target_phys_addr_t addend __attribute__((aligned(8)));
-#else
- target_phys_addr_t addend;
-#endif
+ unsigned long addend;
/* padding to get a power of two size */
uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) -
(sizeof(target_ulong) * 3 +
- ((-sizeof(target_ulong) * 3) & (sizeof(target_phys_addr_t) - 1)) +
- sizeof(target_phys_addr_t))];
+ ((-sizeof(target_ulong) * 3) & (sizeof(unsigned long) - 1)) +
+ sizeof(unsigned long))];
} CPUTLBEntry;
+extern int CPUTLBEntry_wrong_size[sizeof(CPUTLBEntry) == (1 << CPU_TLB_ENTRY_BITS) ? 1 : -1];
+
#define CPU_COMMON_TLB \
/* The meaning of the MMU modes is defined in the target code. */ \
CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
diff --git a/exec.c b/exec.c
index 04e74d2..33854e1 100644
--- a/exec.c
+++ b/exec.c
@@ -2188,7 +2188,7 @@ void tlb_set_page(CPUState *env, target_ulong vaddr,
unsigned int index;
target_ulong address;
target_ulong code_address;
- target_phys_addr_t addend;
+ unsigned long addend;
CPUTLBEntry *te;
CPUWatchpoint *wp;
target_phys_addr_t iotlb;
diff --git a/softmmu_template.h b/softmmu_template.h
index 2f37c34..c2df9ec 100644
--- a/softmmu_template.h
+++ b/softmmu_template.h
@@ -87,7 +87,8 @@ DATA_TYPE REGPARM glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
DATA_TYPE res;
int index;
target_ulong tlb_addr;
- target_phys_addr_t addend;
+ target_phys_addr_t ioaddr;
+ unsigned long addend;
void *retaddr;
/* test if there is match for unaligned or IO access */
@@ -101,8 +102,8 @@ DATA_TYPE REGPARM glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
if ((addr & (DATA_SIZE - 1)) != 0)
goto do_unaligned_access;
retaddr = GETPC();
- addend = env->iotlb[mmu_idx][index];
- res = glue(io_read, SUFFIX)(addend, addr, retaddr);
+ ioaddr = env->iotlb[mmu_idx][index];
+ res = glue(io_read, SUFFIX)(ioaddr, addr, retaddr);
} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
/* slow unaligned access (it spans two pages or IO) */
do_unaligned_access:
@@ -143,7 +144,8 @@ static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
{
DATA_TYPE res, res1, res2;
int index, shift;
- target_phys_addr_t addend;
+ target_phys_addr_t ioaddr;
+ unsigned long addend;
target_ulong tlb_addr, addr1, addr2;
index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
@@ -154,8 +156,8 @@ static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
/* IO access */
if ((addr & (DATA_SIZE - 1)) != 0)
goto do_unaligned_access;
- addend = env->iotlb[mmu_idx][index];
- res = glue(io_read, SUFFIX)(addend, addr, retaddr);
+ ioaddr = env->iotlb[mmu_idx][index];
+ res = glue(io_read, SUFFIX)(ioaddr, addr, retaddr);
} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
do_unaligned_access:
/* slow unaligned access (it spans two pages) */
@@ -224,7 +226,8 @@ void REGPARM glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr,
DATA_TYPE val,
int mmu_idx)
{
- target_phys_addr_t addend;
+ target_phys_addr_t ioaddr;
+ unsigned long addend;
target_ulong tlb_addr;
void *retaddr;
int index;
@@ -238,8 +241,8 @@ void REGPARM glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr,
if ((addr & (DATA_SIZE - 1)) != 0)
goto do_unaligned_access;
retaddr = GETPC();
- addend = env->iotlb[mmu_idx][index];
- glue(io_write, SUFFIX)(addend, val, addr, retaddr);
+ ioaddr = env->iotlb[mmu_idx][index];
+ glue(io_write, SUFFIX)(ioaddr, val, addr, retaddr);
} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
do_unaligned_access:
retaddr = GETPC();
@@ -277,7 +280,8 @@ static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
int mmu_idx,
void *retaddr)
{
- target_phys_addr_t addend;
+ target_phys_addr_t ioaddr;
+ unsigned long addend;
target_ulong tlb_addr;
int index, i;
@@ -289,8 +293,8 @@ static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
/* IO access */
if ((addr & (DATA_SIZE - 1)) != 0)
goto do_unaligned_access;
- addend = env->iotlb[mmu_idx][index];
- glue(io_write, SUFFIX)(addend, val, addr, retaddr);
+ ioaddr = env->iotlb[mmu_idx][index];
+ glue(io_write, SUFFIX)(ioaddr, val, addr, retaddr);
} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
do_unaligned_access:
/* XXX: not efficient, but simple */
diff --git a/targphys.h b/targphys.h
index 99ab23c..95648d6 100644
--- a/targphys.h
+++ b/targphys.h
@@ -5,10 +5,7 @@
#ifdef TARGET_PHYS_ADDR_BITS
/* target_phys_addr_t is the type of a physical address (its size can
- be different from 'target_ulong'). We have sizeof(target_phys_addr)
- = max(sizeof(unsigned long),
- sizeof(size_of_target_physical_address)) because we must pass a
- host pointer to memory operations in some cases */
+ be different from 'target_ulong'). */
#if TARGET_PHYS_ADDR_BITS == 32
typedef uint32_t target_phys_addr_t;
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index 10b9fc1..351efb1 100644
--- a/tcg/mips/tcg-target.c
+++ b/tcg/mips/tcg-target.c
@@ -867,7 +867,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
reloc_pc16(label1_ptr, (tcg_target_long) s->code_ptr);
tcg_out_opc_imm(s, OPC_LW, TCG_REG_A0, TCG_REG_A0,
- offsetof(CPUState, tlb_table[mem_index][0].addend) + addr_meml);
+ offsetof(CPUState, tlb_table[mem_index][0].addend));
tcg_out_opc_reg(s, OPC_ADDU, TCG_REG_V0, TCG_REG_A0, addr_regl);
#else
if (GUEST_BASE == (int16_t)GUEST_BASE) {
@@ -1054,7 +1054,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
reloc_pc16(label1_ptr, (tcg_target_long) s->code_ptr);
tcg_out_opc_imm(s, OPC_LW, TCG_REG_A0, TCG_REG_A0,
- offsetof(CPUState, tlb_table[mem_index][0].addend) + addr_meml);
+ offsetof(CPUState, tlb_table[mem_index][0].addend));
tcg_out_opc_reg(s, OPC_ADDU, TCG_REG_A0, TCG_REG_A0, addr_regl);
#else
if (GUEST_BASE == (int16_t)GUEST_BASE) {
diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c
index 18fdd27..609035a 100644
--- a/tcg/ppc/tcg-target.c
+++ b/tcg/ppc/tcg-target.c
@@ -37,14 +37,6 @@ static uint8_t *tb_ret_addr;
#define FAST_PATH
-#ifdef CONFIG_SOFTMMU
-#if TARGET_PHYS_ADDR_BITS <= 32
-#define ADDEND_OFFSET 0
-#else
-#define ADDEND_OFFSET 4
-#endif
-#endif
-
#ifndef GUEST_BASE
#define GUEST_BASE 0
#endif
@@ -648,7 +640,7 @@ static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
tcg_out32 (s, (LWZ
| RT (r0)
| RA (r0)
- | (ADDEND_OFFSET + offsetof (CPUTLBEntry, addend)
+ | (offsetof (CPUTLBEntry, addend)
- offsetof (CPUTLBEntry, addr_read))
));
/* r0 = env->tlb_table[mem_index][index].addend */
@@ -847,7 +839,7 @@ static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
tcg_out32 (s, (LWZ
| RT (r0)
| RA (r0)
- | (ADDEND_OFFSET + offsetof (CPUTLBEntry, addend)
+ | (offsetof (CPUTLBEntry, addend)
- offsetof (CPUTLBEntry, addr_write))
));
/* r0 = env->tlb_table[mem_index][index].addend */
diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
index 4d6e68c..2725c6e 100644
--- a/tcg/ppc64/tcg-target.c
+++ b/tcg/ppc64/tcg-target.c
@@ -28,14 +28,6 @@ static uint8_t *tb_ret_addr;
#define FAST_PATH
-#ifdef CONFIG_SOFTMMU
-#if TARGET_PHYS_ADDR_BITS == 32
-#define LD_ADDEND LWZ
-#else
-#define LD_ADDEND LD
-#endif
-#endif
-
#if TARGET_LONG_BITS == 32
#define LD_ADDR LWZU
#define CMP_L 0
@@ -684,7 +676,7 @@ static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
#endif
/* r0 now contains &env->tlb_table[mem_index][index].addr_read */
- tcg_out32 (s, (LD_ADDEND
+ tcg_out32 (s, (LD
| RT (r0)
| RA (r0)
| (offsetof (CPUTLBEntry, addend)
@@ -812,7 +804,7 @@ static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
#endif
- tcg_out32 (s, (LD_ADDEND
+ tcg_out32 (s, (LD
| RT (r0)
| RA (r0)
| (offsetof (CPUTLBEntry, addend)
diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index 6d8410c..e460d44 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -726,13 +726,7 @@ static const void * const qemu_st_helpers[4] = {
#endif
#if defined(CONFIG_SOFTMMU)
-#if TARGET_PHYS_ADDR_BITS == 32
-#define TARGET_ADDEND_LD_OP LDUW
-#else
-#define TARGET_ADDEND_LD_OP LDX
-#endif
-#else
-#if TARGET_ABI_BITS == 32
+#if HOST_LONG_BITS == 32
#define TARGET_ADDEND_LD_OP LDUW
#else
#define TARGET_ADDEND_LD_OP LDX
generated by cgit v1.1 at 2024-12-26 06:45:52 +0000