diff options
| -rw-r--r-- | target/ppc/excp_helper.c | 7 | ||||
| -rw-r--r-- | target/ppc/helper_regs.h | 17 |
2 files changed, 18 insertions, 6 deletions
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index e6009e7..37d2410 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -207,7 +207,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) "Entering checkstop state\n"); } cs->halted = 1; - cs->interrupt_request |= CPU_INTERRUPT_EXITTB; + cpu_interrupt_exittb(cs); } if (env->msr_mask & MSR_HVB) { /* ISA specifies HV, but can be delivered to guest with HV clear @@ -940,7 +940,7 @@ void helper_store_msr(CPUPPCState *env, target_ulong val) if (excp != 0) { CPUState *cs = CPU(ppc_env_get_cpu(env)); - cs->interrupt_request |= CPU_INTERRUPT_EXITTB; + cpu_interrupt_exittb(cs); raise_exception(env, excp); } } @@ -995,8 +995,7 @@ static inline void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr) /* No need to raise an exception here, * as rfi is always the last insn of a TB */ - cs->interrupt_request |= CPU_INTERRUPT_EXITTB; - + cpu_interrupt_exittb(cs); /* Reset the reservation */ env->reserve_addr = -1; diff --git a/target/ppc/helper_regs.h b/target/ppc/helper_regs.h index 2627a70..84fd30c 100644 --- a/target/ppc/helper_regs.h +++ b/target/ppc/helper_regs.h @@ -20,6 +20,8 @@ #ifndef HELPER_REGS_H #define HELPER_REGS_H +#include "qemu/main-loop.h" + /* Swap temporary saved registers with GPRs */ static inline void hreg_swap_gpr_tgpr(CPUPPCState *env) { @@ -96,6 +98,17 @@ static inline void hreg_compute_hflags(CPUPPCState *env) env->hflags |= env->hflags_nmsr; } +static inline void cpu_interrupt_exittb(CPUState *cs) +{ + if (!qemu_mutex_iothread_locked()) { + qemu_mutex_lock_iothread(); + cpu_interrupt(cs, CPU_INTERRUPT_EXITTB); + qemu_mutex_unlock_iothread(); + } else { + cpu_interrupt(cs, CPU_INTERRUPT_EXITTB); + } +} + static inline int hreg_store_msr(CPUPPCState *env, target_ulong value, int alter_hv) { @@ -114,11 +127,11 @@ static inline int hreg_store_msr(CPUPPCState *env, target_ulong value, } if (((value >> MSR_IR) & 1) != msr_ir || ((value >> MSR_DR) & 1) != msr_dr) { - cs->interrupt_request |= CPU_INTERRUPT_EXITTB; + cpu_interrupt_exittb(cs); } if ((env->mmu_model & POWERPC_MMU_BOOKE) && ((value >> MSR_GS) & 1) != msr_gs) { - cs->interrupt_request |= CPU_INTERRUPT_EXITTB; + cpu_interrupt_exittb(cs); } if (unlikely((env->flags & POWERPC_FLAG_TGPR) && ((value ^ env->msr) & (1 << MSR_TGPR)))) { |