diff options
| -rw-r--r-- | target-mips/op.c | 11 | ||||
| -rw-r--r-- | target-mips/translate.c | 1 |
2 files changed, 9 insertions, 3 deletions
diff --git a/target-mips/op.c b/target-mips/op.c index aec6a02..d7f0306 100644 --- a/target-mips/op.c +++ b/target-mips/op.c @@ -1444,13 +1444,16 @@ void op_mtc0_config2 (void) void op_mtc0_watchlo0 (void) { - env->CP0_WatchLo = (int32_t)T0; + /* Watch exceptions for instructions, data loads, data stores + not implemented. */ + env->CP0_WatchLo = (int32_t)(T0 & ~0x7); RETURN(); } void op_mtc0_watchhi0 (void) { - env->CP0_WatchHi = T0 & 0x40FF0FF8; + env->CP0_WatchHi = (T0 & 0x40FF0FF8); + env->CP0_WatchHi &= ~(env->CP0_WatchHi & T0 & 0x7); RETURN(); } @@ -1620,7 +1623,9 @@ void op_dmtc0_epc (void) void op_dmtc0_watchlo0 (void) { - env->CP0_WatchLo = T0; + /* Watch exceptions for instructions, data loads, data stores + not implemented. */ + env->CP0_WatchLo = T0 & ~0x7; RETURN(); } diff --git a/target-mips/translate.c b/target-mips/translate.c index e5eff06..a1af8ab 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -5406,6 +5406,7 @@ void cpu_reset (CPUMIPSState *env) env->CP0_EBase = 0x80000000; env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL); env->CP0_WatchLo = 0; + env->CP0_WatchHi = 0; /* Count register increments in debug mode, EJTAG version 1 */ env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER); #endif |