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-rw-r--r--hw/intc/riscv_aplic.c6
-rw-r--r--hw/riscv/virt-acpi-build.c25
-rw-r--r--linux-user/strace.list3
-rw-r--r--target/riscv/csr.c15
-rw-r--r--target/riscv/insn_trans/trans_rvv.c.inc323
-rw-r--r--target/riscv/op_helper.c15
-rw-r--r--target/riscv/pmp.c7
-rw-r--r--tests/data/acpi/riscv64/virt/APICbin116 -> 116 bytes
-rw-r--r--tests/data/acpi/riscv64/virt/FACPbin276 -> 276 bytes
9 files changed, 90 insertions, 304 deletions
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index 4fa5f75..a1d9fa5 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -628,7 +628,7 @@ static void riscv_aplic_request(void *opaque, int irq, int level)
static uint64_t riscv_aplic_read(void *opaque, hwaddr addr, unsigned size)
{
- uint32_t irq, word, idc;
+ uint32_t irq, word, idc, sm;
RISCVAPLICState *aplic = opaque;
/* Reads must be 4 byte words */
@@ -696,6 +696,10 @@ static uint64_t riscv_aplic_read(void *opaque, hwaddr addr, unsigned size)
} else if ((APLIC_TARGET_BASE <= addr) &&
(addr < (APLIC_TARGET_BASE + (aplic->num_irqs - 1) * 4))) {
irq = ((addr - APLIC_TARGET_BASE) >> 2) + 1;
+ sm = aplic->sourcecfg[irq] & APLIC_SOURCECFG_SM_MASK;
+ if (sm == APLIC_SOURCECFG_SM_INACTIVE) {
+ return 0;
+ }
return aplic->target[irq];
} else if (!aplic->msimode && (APLIC_IDC_BASE <= addr) &&
(addr < (APLIC_IDC_BASE + aplic->num_harts * APLIC_IDC_SIZE))) {
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index ee1416d..f1406cb 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -270,11 +270,8 @@ spcr_setup(GArray *table_data, BIOSLinker *linker, RISCVVirtState *s)
#define RHCT_NODE_ARRAY_OFFSET 56
/*
- * ACPI spec, Revision 6.5+
- * 5.2.36 RISC-V Hart Capabilities Table (RHCT)
- * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/16
- * https://drive.google.com/file/d/1nP3nFiH4jkPMp6COOxP6123DCZKR-tia/view
- * https://drive.google.com/file/d/1sKbOa8m1UZw1JkquZYe3F1zQBN1xXsaf/view
+ * ACPI spec, Revision 6.6
+ * 5.2.37 RISC-V Hart Capabilities Table (RHCT)
*/
static void build_rhct(GArray *table_data,
BIOSLinker *linker,
@@ -421,7 +418,10 @@ static void build_rhct(GArray *table_data,
acpi_table_end(linker, &table);
}
-/* FADT */
+/*
+ * ACPI spec, Revision 6.6
+ * 5.2.9 Fixed ACPI Description Table (MADT)
+ */
static void build_fadt_rev6(GArray *table_data,
BIOSLinker *linker,
RISCVVirtState *s,
@@ -429,7 +429,7 @@ static void build_fadt_rev6(GArray *table_data,
{
AcpiFadtData fadt = {
.rev = 6,
- .minor_ver = 5,
+ .minor_ver = 6,
.flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI,
.xdsdt_tbl_offset = &dsdt_tbl_offset,
};
@@ -508,11 +508,8 @@ static void build_dsdt(GArray *table_data,
}
/*
- * ACPI spec, Revision 6.5+
+ * ACPI spec, Revision 6.6
* 5.2.12 Multiple APIC Description Table (MADT)
- * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/15
- * https://drive.google.com/file/d/1R6k4MshhN3WTT-hwqAquu5nX6xSEqK2l/view
- * https://drive.google.com/file/d/1oMGPyOD58JaPgMl1pKasT-VKsIKia7zR/view
*/
static void build_madt(GArray *table_data,
BIOSLinker *linker,
@@ -537,7 +534,7 @@ static void build_madt(GArray *table_data,
hart_index_bits = imsic_num_bits(imsic_max_hart_per_socket);
- AcpiTable table = { .sig = "APIC", .rev = 6, .oem_id = s->oem_id,
+ AcpiTable table = { .sig = "APIC", .rev = 7, .oem_id = s->oem_id,
.oem_table_id = s->oem_table_id };
acpi_table_begin(&table, table_data);
@@ -812,10 +809,8 @@ static void build_rimt(GArray *table_data, BIOSLinker *linker,
}
/*
- * ACPI spec, Revision 6.5+
+ * ACPI spec, Revision 6.6
* 5.2.16 System Resource Affinity Table (SRAT)
- * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/25
- * https://drive.google.com/file/d/1YTdDx2IPm5IeZjAW932EYU-tUtgS08tX/view
*/
static void
build_srat(GArray *table_data, BIOSLinker *linker, RISCVVirtState *vms)
diff --git a/linux-user/strace.list b/linux-user/strace.list
index fdf94ef..ab81835 100644
--- a/linux-user/strace.list
+++ b/linux-user/strace.list
@@ -1716,3 +1716,6 @@
{ TARGET_NR_clock_gettime64, "clock_gettime64" , NULL, print_clock_gettime64,
print_syscall_ret_clock_gettime64 },
#endif
+#ifdef TARGET_NR_riscv_hwprobe
+{ TARGET_NR_riscv_hwprobe, "riscv_hwprobe" , "%s(%p,%d,%d,%d,%d,%d)", NULL, NULL },
+#endif
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 8631be9..8842e07 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -374,8 +374,11 @@ static RISCVException aia_smode(CPURISCVState *env, int csrno)
static RISCVException aia_smode32(CPURISCVState *env, int csrno)
{
int ret;
+ int csr_priv = get_field(csrno, 0x300);
- if (!riscv_cpu_cfg(env)->ext_ssaia) {
+ if (csr_priv == PRV_M && !riscv_cpu_cfg(env)->ext_smaia) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ } else if (!riscv_cpu_cfg(env)->ext_ssaia) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -5577,7 +5580,7 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
csr_priv = get_field(csrno, 0x300);
if (!env->debugger && (effective_priv < csr_priv)) {
- if (csr_priv == (PRV_S + 1) && env->virt_enabled) {
+ if (csr_priv <= (PRV_S + 1) && env->virt_enabled) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
}
return RISCV_EXCP_ILLEGAL_INST;
@@ -5862,8 +5865,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
NULL, read_mstatus_i128 },
[CSR_MISA] = { "misa", any, read_misa, write_misa,
NULL, read_misa_i128 },
- [CSR_MIDELEG] = { "mideleg", any, NULL, NULL, rmw_mideleg },
- [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg },
+ [CSR_MIDELEG] = { "mideleg", smode, NULL, NULL, rmw_mideleg },
+ [CSR_MEDELEG] = { "medeleg", smode, read_medeleg, write_medeleg },
[CSR_MIE] = { "mie", any, NULL, NULL, rmw_mie },
[CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec },
[CSR_MCOUNTEREN] = { "mcounteren", umode, read_mcounteren,
@@ -5871,7 +5874,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MSTATUSH] = { "mstatush", any32, read_mstatush,
write_mstatush },
- [CSR_MEDELEGH] = { "medelegh", any32, read_zero, write_ignore,
+ [CSR_MEDELEGH] = { "medelegh", smode32, read_zero, write_ignore,
.min_priv_ver = PRIV_VERSION_1_13_0 },
[CSR_HEDELEGH] = { "hedelegh", hmode32, read_hedelegh, write_hedelegh,
.min_priv_ver = PRIV_VERSION_1_13_0 },
@@ -5911,7 +5914,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MVIP] = { "mvip", aia_any, NULL, NULL, rmw_mvip },
/* Machine-Level High-Half CSRs (AIA) */
- [CSR_MIDELEGH] = { "midelegh", aia_any32, NULL, NULL, rmw_midelegh },
+ [CSR_MIDELEGH] = { "midelegh", aia_smode32, NULL, NULL, rmw_midelegh },
[CSR_MIEH] = { "mieh", aia_any32, NULL, NULL, rmw_mieh },
[CSR_MVIENH] = { "mvienh", aia_any32, NULL, NULL, rmw_mvienh },
[CSR_MVIPH] = { "mviph", aia_any32, NULL, NULL, rmw_mviph },
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 610bf9f..71f98fb 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -864,286 +864,32 @@ GEN_VEXT_TRANS(vlm_v, MO_8, vlm_v, ld_us_mask_op, ld_us_mask_check)
GEN_VEXT_TRANS(vsm_v, MO_8, vsm_v, st_us_mask_op, st_us_mask_check)
/*
- * MAXSZ returns the maximum vector size can be operated in bytes,
- * which is used in GVEC IR when vl_eq_vlmax flag is set to true
- * to accelerate vector operation.
- */
-static inline uint32_t MAXSZ(DisasContext *s)
-{
- int max_sz = s->cfg_ptr->vlenb << 3;
- return max_sz >> (3 - s->lmul);
-}
-
-static inline uint32_t get_log2(uint32_t a)
-{
- uint32_t i = 0;
- for (; a > 0;) {
- a >>= 1;
- i++;
- }
- return i;
-}
-
-typedef void gen_tl_ldst(TCGv, TCGv_ptr, tcg_target_long);
-
-/*
- * Simulate the strided load/store main loop:
- *
- * for (i = env->vstart; i < env->vl; env->vstart = ++i) {
- * k = 0;
- * while (k < nf) {
- * if (!vm && !vext_elem_mask(v0, i)) {
- * vext_set_elems_1s(vd, vma, (i + k * max_elems) * esz,
- * (i + k * max_elems + 1) * esz);
- * k++;
- * continue;
- * }
- * target_ulong addr = base + stride * i + (k << log2_esz);
- * ldst(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
- * k++;
- * }
- * }
- */
-static void gen_ldst_stride_main_loop(DisasContext *s, TCGv dest, uint32_t rs1,
- uint32_t rs2, uint32_t vm, uint32_t nf,
- gen_tl_ldst *ld_fn, gen_tl_ldst *st_fn,
- bool is_load)
-{
- TCGv addr = tcg_temp_new();
- TCGv base = get_gpr(s, rs1, EXT_NONE);
- TCGv stride = get_gpr(s, rs2, EXT_NONE);
-
- TCGv i = tcg_temp_new();
- TCGv i_esz = tcg_temp_new();
- TCGv k = tcg_temp_new();
- TCGv k_esz = tcg_temp_new();
- TCGv k_max = tcg_temp_new();
- TCGv mask = tcg_temp_new();
- TCGv mask_offs = tcg_temp_new();
- TCGv mask_offs_64 = tcg_temp_new();
- TCGv mask_elem = tcg_temp_new();
- TCGv mask_offs_rem = tcg_temp_new();
- TCGv vreg = tcg_temp_new();
- TCGv dest_offs = tcg_temp_new();
- TCGv stride_offs = tcg_temp_new();
-
- uint32_t max_elems = MAXSZ(s) >> s->sew;
-
- TCGLabel *start = gen_new_label();
- TCGLabel *end = gen_new_label();
- TCGLabel *start_k = gen_new_label();
- TCGLabel *inc_k = gen_new_label();
- TCGLabel *end_k = gen_new_label();
-
- MemOp atomicity = MO_ATOM_NONE;
- if (s->sew == 0) {
- atomicity = MO_ATOM_NONE;
- } else {
- atomicity = MO_ATOM_IFALIGN_PAIR;
- }
-
- mark_vs_dirty(s);
-
- tcg_gen_addi_tl(mask, (TCGv)tcg_env, vreg_ofs(s, 0));
-
- /* Start of outer loop. */
- tcg_gen_mov_tl(i, cpu_vstart);
- gen_set_label(start);
- tcg_gen_brcond_tl(TCG_COND_GE, i, cpu_vl, end);
- tcg_gen_shli_tl(i_esz, i, s->sew);
- /* Start of inner loop. */
- tcg_gen_movi_tl(k, 0);
- gen_set_label(start_k);
- tcg_gen_brcond_tl(TCG_COND_GE, k, tcg_constant_tl(nf), end_k);
- /*
- * If we are in mask agnostic regime and the operation is not unmasked we
- * set the inactive elements to 1.
- */
- if (!vm && s->vma) {
- TCGLabel *active_element = gen_new_label();
- /* (i + k * max_elems) * esz */
- tcg_gen_shli_tl(mask_offs, k, get_log2(max_elems << s->sew));
- tcg_gen_add_tl(mask_offs, mask_offs, i_esz);
-
- /*
- * Check whether the i bit of the mask is 0 or 1.
- *
- * static inline int vext_elem_mask(void *v0, int index)
- * {
- * int idx = index / 64;
- * int pos = index % 64;
- * return (((uint64_t *)v0)[idx] >> pos) & 1;
- * }
- */
- tcg_gen_shri_tl(mask_offs_64, mask_offs, 3);
- tcg_gen_add_tl(mask_offs_64, mask_offs_64, mask);
- tcg_gen_ld_i64((TCGv_i64)mask_elem, (TCGv_ptr)mask_offs_64, 0);
- tcg_gen_rem_tl(mask_offs_rem, mask_offs, tcg_constant_tl(8));
- tcg_gen_shr_tl(mask_elem, mask_elem, mask_offs_rem);
- tcg_gen_andi_tl(mask_elem, mask_elem, 1);
- tcg_gen_brcond_tl(TCG_COND_NE, mask_elem, tcg_constant_tl(0),
- active_element);
- /*
- * Set masked-off elements in the destination vector register to 1s.
- * Store instructions simply skip this bit as memory ops access memory
- * only for active elements.
- */
- if (is_load) {
- tcg_gen_shli_tl(mask_offs, mask_offs, s->sew);
- tcg_gen_add_tl(mask_offs, mask_offs, dest);
- st_fn(tcg_constant_tl(-1), (TCGv_ptr)mask_offs, 0);
- }
- tcg_gen_br(inc_k);
- gen_set_label(active_element);
- }
- /*
- * The element is active, calculate the address with stride:
- * target_ulong addr = base + stride * i + (k << log2_esz);
- */
- tcg_gen_mul_tl(stride_offs, stride, i);
- tcg_gen_shli_tl(k_esz, k, s->sew);
- tcg_gen_add_tl(stride_offs, stride_offs, k_esz);
- tcg_gen_add_tl(addr, base, stride_offs);
- /* Calculate the offset in the dst/src vector register. */
- tcg_gen_shli_tl(k_max, k, get_log2(max_elems));
- tcg_gen_add_tl(dest_offs, i, k_max);
- tcg_gen_shli_tl(dest_offs, dest_offs, s->sew);
- tcg_gen_add_tl(dest_offs, dest_offs, dest);
- if (is_load) {
- tcg_gen_qemu_ld_tl(vreg, addr, s->mem_idx, MO_LE | s->sew | atomicity);
- st_fn((TCGv)vreg, (TCGv_ptr)dest_offs, 0);
- } else {
- ld_fn((TCGv)vreg, (TCGv_ptr)dest_offs, 0);
- tcg_gen_qemu_st_tl(vreg, addr, s->mem_idx, MO_LE | s->sew | atomicity);
- }
- /*
- * We don't execute the load/store above if the element was inactive.
- * We jump instead directly to incrementing k and continuing the loop.
- */
- if (!vm && s->vma) {
- gen_set_label(inc_k);
- }
- tcg_gen_addi_tl(k, k, 1);
- tcg_gen_br(start_k);
- /* End of the inner loop. */
- gen_set_label(end_k);
-
- tcg_gen_addi_tl(i, i, 1);
- tcg_gen_mov_tl(cpu_vstart, i);
- tcg_gen_br(start);
-
- /* End of the outer loop. */
- gen_set_label(end);
-
- return;
-}
-
-
-/*
- * Set the tail bytes of the strided loads/stores to 1:
- *
- * for (k = 0; k < nf; ++k) {
- * cnt = (k * max_elems + vl) * esz;
- * tot = (k * max_elems + max_elems) * esz;
- * for (i = cnt; i < tot; i += esz) {
- * store_1s(-1, vd[vl+i]);
- * }
- * }
+ *** stride load and store
*/
-static void gen_ldst_stride_tail_loop(DisasContext *s, TCGv dest, uint32_t nf,
- gen_tl_ldst *st_fn)
-{
- TCGv i = tcg_temp_new();
- TCGv k = tcg_temp_new();
- TCGv tail_cnt = tcg_temp_new();
- TCGv tail_tot = tcg_temp_new();
- TCGv tail_addr = tcg_temp_new();
-
- TCGLabel *start = gen_new_label();
- TCGLabel *end = gen_new_label();
- TCGLabel *start_i = gen_new_label();
- TCGLabel *end_i = gen_new_label();
-
- uint32_t max_elems_b = MAXSZ(s);
- uint32_t esz = 1 << s->sew;
-
- /* Start of the outer loop. */
- tcg_gen_movi_tl(k, 0);
- tcg_gen_shli_tl(tail_cnt, cpu_vl, s->sew);
- tcg_gen_movi_tl(tail_tot, max_elems_b);
- tcg_gen_add_tl(tail_addr, dest, tail_cnt);
- gen_set_label(start);
- tcg_gen_brcond_tl(TCG_COND_GE, k, tcg_constant_tl(nf), end);
- /* Start of the inner loop. */
- tcg_gen_mov_tl(i, tail_cnt);
- gen_set_label(start_i);
- tcg_gen_brcond_tl(TCG_COND_GE, i, tail_tot, end_i);
- /* store_1s(-1, vd[vl+i]); */
- st_fn(tcg_constant_tl(-1), (TCGv_ptr)tail_addr, 0);
- tcg_gen_addi_tl(tail_addr, tail_addr, esz);
- tcg_gen_addi_tl(i, i, esz);
- tcg_gen_br(start_i);
- /* End of the inner loop. */
- gen_set_label(end_i);
- /* Update the counts */
- tcg_gen_addi_tl(tail_cnt, tail_cnt, max_elems_b);
- tcg_gen_addi_tl(tail_tot, tail_cnt, max_elems_b);
- tcg_gen_addi_tl(k, k, 1);
- tcg_gen_br(start);
- /* End of the outer loop. */
- gen_set_label(end);
-
- return;
-}
+typedef void gen_helper_ldst_stride(TCGv_ptr, TCGv_ptr, TCGv,
+ TCGv, TCGv_env, TCGv_i32);
static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
- uint32_t data, DisasContext *s, bool is_load)
+ uint32_t data, gen_helper_ldst_stride *fn,
+ DisasContext *s)
{
- if (!s->vstart_eq_zero) {
- return false;
- }
-
- TCGv dest = tcg_temp_new();
-
- uint32_t nf = FIELD_EX32(data, VDATA, NF);
- uint32_t vm = FIELD_EX32(data, VDATA, VM);
-
- /* Destination register and mask register */
- tcg_gen_addi_tl(dest, (TCGv)tcg_env, vreg_ofs(s, vd));
-
- /*
- * Select the appropriate load/tore to retrieve data from the vector
- * register given a specific sew.
- */
- static gen_tl_ldst * const ld_fns[4] = {
- tcg_gen_ld8u_tl, tcg_gen_ld16u_tl,
- tcg_gen_ld32u_tl, tcg_gen_ld_tl
- };
-
- static gen_tl_ldst * const st_fns[4] = {
- tcg_gen_st8_tl, tcg_gen_st16_tl,
- tcg_gen_st32_tl, tcg_gen_st_tl
- };
+ TCGv_ptr dest, mask;
+ TCGv base, stride;
+ TCGv_i32 desc;
- gen_tl_ldst *ld_fn = ld_fns[s->sew];
- gen_tl_ldst *st_fn = st_fns[s->sew];
+ dest = tcg_temp_new_ptr();
+ mask = tcg_temp_new_ptr();
+ base = get_gpr(s, rs1, EXT_NONE);
+ stride = get_gpr(s, rs2, EXT_NONE);
+ desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
+ s->cfg_ptr->vlenb, data));
- if (ld_fn == NULL || st_fn == NULL) {
- return false;
- }
+ tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
+ tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
mark_vs_dirty(s);
- gen_ldst_stride_main_loop(s, dest, rs1, rs2, vm, nf, ld_fn, st_fn, is_load);
-
- tcg_gen_movi_tl(cpu_vstart, 0);
-
- /*
- * Set the tail bytes to 1 if tail agnostic:
- */
- if (s->vta != 0 && is_load) {
- gen_ldst_stride_tail_loop(s, dest, nf, st_fn);
- }
+ fn(dest, mask, base, stride, tcg_env, desc);
finalize_rvv_inst(s);
return true;
@@ -1152,6 +898,16 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
{
uint32_t data = 0;
+ gen_helper_ldst_stride *fn;
+ static gen_helper_ldst_stride * const fns[4] = {
+ gen_helper_vlse8_v, gen_helper_vlse16_v,
+ gen_helper_vlse32_v, gen_helper_vlse64_v
+ };
+
+ fn = fns[eew];
+ if (fn == NULL) {
+ return false;
+ }
uint8_t emul = vext_get_emul(s, eew);
data = FIELD_DP32(data, VDATA, VM, a->vm);
@@ -1159,7 +915,7 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
data = FIELD_DP32(data, VDATA, NF, a->nf);
data = FIELD_DP32(data, VDATA, VTA, s->vta);
data = FIELD_DP32(data, VDATA, VMA, s->vma);
- return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, s, true);
+ return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
}
static bool ld_stride_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
@@ -1177,13 +933,23 @@ GEN_VEXT_TRANS(vlse64_v, MO_64, rnfvm, ld_stride_op, ld_stride_check)
static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
{
uint32_t data = 0;
+ gen_helper_ldst_stride *fn;
+ static gen_helper_ldst_stride * const fns[4] = {
+ /* masked stride store */
+ gen_helper_vsse8_v, gen_helper_vsse16_v,
+ gen_helper_vsse32_v, gen_helper_vsse64_v
+ };
uint8_t emul = vext_get_emul(s, eew);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, emul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
+ fn = fns[eew];
+ if (fn == NULL) {
+ return false;
+ }
- return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, s, false);
+ return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
}
static bool st_stride_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
@@ -1534,6 +1300,17 @@ GEN_LDST_WHOLE_TRANS(vs8r_v, int8_t, 8, false)
*** Vector Integer Arithmetic Instructions
*/
+/*
+ * MAXSZ returns the maximum vector size can be operated in bytes,
+ * which is used in GVEC IR when vl_eq_vlmax flag is set to true
+ * to accelerate vector operation.
+ */
+static inline uint32_t MAXSZ(DisasContext *s)
+{
+ int max_sz = s->cfg_ptr->vlenb * 8;
+ return max_sz >> (3 - s->lmul);
+}
+
static bool opivv_check(DisasContext *s, arg_rmrr *a)
{
return require_rvv(s) &&
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 15460bf..110292e 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -355,21 +355,22 @@ target_ulong helper_sret(CPURISCVState *env)
}
static void check_ret_from_m_mode(CPURISCVState *env, target_ulong retpc,
- target_ulong prev_priv)
+ target_ulong prev_priv,
+ uintptr_t ra)
{
if (!(env->priv >= PRV_M)) {
- riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra);
}
if (!riscv_cpu_allow_16bit_insn(&env_archcpu(env)->cfg,
env->priv_ver,
env->misa_ext) && (retpc & 0x3)) {
- riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
+ riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, ra);
}
if (riscv_cpu_cfg(env)->pmp &&
!pmp_get_num_rules(env) && (prev_priv != PRV_M)) {
- riscv_raise_exception(env, RISCV_EXCP_INST_ACCESS_FAULT, GETPC());
+ riscv_raise_exception(env, RISCV_EXCP_INST_ACCESS_FAULT, ra);
}
}
static target_ulong ssdbltrp_mxret(CPURISCVState *env, target_ulong mstatus,
@@ -394,8 +395,9 @@ target_ulong helper_mret(CPURISCVState *env)
target_ulong retpc = env->mepc & get_xepc_mask(env);
uint64_t mstatus = env->mstatus;
target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP);
+ uintptr_t ra = GETPC();
- check_ret_from_m_mode(env, retpc, prev_priv);
+ check_ret_from_m_mode(env, retpc, prev_priv, ra);
target_ulong prev_virt = get_field(env->mstatus, MSTATUS_MPV) &&
(prev_priv != PRV_M);
@@ -443,8 +445,9 @@ target_ulong helper_mnret(CPURISCVState *env)
target_ulong retpc = env->mnepc;
target_ulong prev_priv = get_field(env->mnstatus, MNSTATUS_MNPP);
target_ulong prev_virt;
+ uintptr_t ra = GETPC();
- check_ret_from_m_mode(env, retpc, prev_priv);
+ check_ret_from_m_mode(env, retpc, prev_priv, ra);
prev_virt = get_field(env->mnstatus, MNSTATUS_MNPV) &&
(prev_priv != PRV_M);
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 3540327..72f1372 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -211,11 +211,12 @@ void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index)
break;
case PMP_AMATCH_TOR:
- sa = prev_addr << 2; /* shift up from [xx:0] to [xx+2:2] */
- ea = (this_addr << 2) - 1u;
- if (sa > ea) {
+ if (prev_addr >= this_addr) {
sa = ea = 0u;
+ break;
}
+ sa = prev_addr << 2; /* shift up from [xx:0] to [xx+2:2] */
+ ea = (this_addr << 2) - 1u;
break;
case PMP_AMATCH_NA4:
diff --git a/tests/data/acpi/riscv64/virt/APIC b/tests/data/acpi/riscv64/virt/APIC
index 66a25df..3fb5b75 100644
--- a/tests/data/acpi/riscv64/virt/APIC
+++ b/tests/data/acpi/riscv64/virt/APIC
Binary files differ
diff --git a/tests/data/acpi/riscv64/virt/FACP b/tests/data/acpi/riscv64/virt/FACP
index a5276b6..78e1b14 100644
--- a/tests/data/acpi/riscv64/virt/FACP
+++ b/tests/data/acpi/riscv64/virt/FACP
Binary files differ
generated by cgit v1.1 at 2025-08-01 14:09:58 +0000