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author | Richard Henderson <richard.henderson@linaro.org> | 2023-04-12 13:43:25 +0200 |
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committer | Alistair Francis <alistair.francis@wdc.com> | 2023-05-05 10:49:50 +1000 |
commit | eaecd473ca0e91c59dcf8a9e58b32518ed6b1bdf (patch) | |
tree | 9111c28628dd9fc12586377ebc886cb38dbdfd65 /util/qemu-timer-common.c | |
parent | 696bacde957bc5cdabc7710abc316ef56184d928 (diff) | |
download | qemu-eaecd473ca0e91c59dcf8a9e58b32518ed6b1bdf.zip qemu-eaecd473ca0e91c59dcf8a9e58b32518ed6b1bdf.tar.gz qemu-eaecd473ca0e91c59dcf8a9e58b32518ed6b1bdf.tar.bz2 |
target/riscv: Check SUM in the correct register
Table 9.5 "Effect of MPRV..." specifies that MPV=1 uses VS-level
vsstatus.SUM instead of HS-level sstatus.SUM.
For HLV/HSV instructions, the HS-level register does not apply, but
the VS-level register presumably does, though this is not mentioned
explicitly in the manual. However, it matches the behavior for MPV.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-18-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-18-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'util/qemu-timer-common.c')
0 files changed, 0 insertions, 0 deletions