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| author | Xuzhou Cheng <xuzhou.cheng@windriver.com> | 2021-03-03 21:52:52 +0800 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-03-10 13:54:51 +0000 |
| commit | 668351a54883b6283e7ae94daf4d4eca1a071158 (patch) | |
| tree | d44541fb944bcb9d809bf9df774a141072f88dd2 /util/dbus.c | |
| parent | 21bce3717e2cb70e3bea06e8684bae111c9f4dda (diff) | |
| download | qemu-668351a54883b6283e7ae94daf4d4eca1a071158.zip qemu-668351a54883b6283e7ae94daf4d4eca1a071158.tar.gz qemu-668351a54883b6283e7ae94daf4d4eca1a071158.tar.bz2 | |
hw/arm: xlnx-zynqmp: Connect a Xilinx CSU DMA module for QSPI
Add a Xilinx CSU DMA module to ZynqMP SoC, and connent the stream
link of GQSPI to CSU DMA.
Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20210303135254.3970-4-bmeng.cn@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'util/dbus.c')
0 files changed, 0 insertions, 0 deletions