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| author | Richard Henderson <rth@twiddle.net> | 2014-03-14 22:24:57 -0400 |
|---|---|---|
| committer | Richard Henderson <rth@redhat.com> | 2014-04-16 12:12:32 -0400 |
| commit | 661f7fa4b088f2734050a751dd9d1d836b49e981 (patch) | |
| tree | 94e0c8058361948716e71922bceedfd5243b00df /user-exec.c | |
| parent | 851627352c52b5beebf119785885391fa05a44c5 (diff) | |
| download | qemu-661f7fa4b088f2734050a751dd9d1d836b49e981.zip qemu-661f7fa4b088f2734050a751dd9d1d836b49e981.tar.gz qemu-661f7fa4b088f2734050a751dd9d1d836b49e981.tar.bz2 | |
tcg-aarch64: Properly detect SIGSEGV writes
Since the kernel doesn't pass any info on the reason for the fault,
disassemble the instruction to detect a store.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'user-exec.c')
| -rw-r--r-- | user-exec.c | 25 |
1 files changed, 19 insertions, 6 deletions
diff --git a/user-exec.c b/user-exec.c index bc58056..8ed6fec 100644 --- a/user-exec.c +++ b/user-exec.c @@ -465,16 +465,29 @@ int cpu_signal_handler(int host_signum, void *pinfo, #elif defined(__aarch64__) -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) +int cpu_signal_handler(int host_signum, void *pinfo, void *puc) { siginfo_t *info = pinfo; struct ucontext *uc = puc; - uint64_t pc; - int is_write = 0; /* XXX how to determine? */ + uintptr_t pc = uc->uc_mcontext.pc; + uint32_t insn = *(uint32_t *)pc; + bool is_write; - pc = uc->uc_mcontext.pc; - return handle_cpu_signal(pc, (uint64_t)info->si_addr, + /* XXX: need kernel patch to get write flag faster. */ + is_write = ( (insn & 0xbfff0000) == 0x0c000000 /* C3.3.1 */ + || (insn & 0xbfe00000) == 0x0c800000 /* C3.3.2 */ + || (insn & 0xbfdf0000) == 0x0d000000 /* C3.3.3 */ + || (insn & 0xbfc00000) == 0x0d800000 /* C3.3.4 */ + || (insn & 0x3f400000) == 0x08000000 /* C3.3.6 */ + || (insn & 0x3bc00000) == 0x39000000 /* C3.3.13 */ + || (insn & 0x3fc00000) == 0x3d800000 /* ... 128bit */ + /* Ingore bits 10, 11 & 21, controlling indexing. */ + || (insn & 0x3bc00000) == 0x38000000 /* C3.3.8-12 */ + || (insn & 0x3fe00000) == 0x3c800000 /* ... 128bit */ + /* Ignore bits 23 & 24, controlling indexing. */ + || (insn & 0x3a400000) == 0x28000000); /* C3.3.7,14-16 */ + + return handle_cpu_signal(pc, (uintptr_t)info->si_addr, is_write, &uc->uc_sigmask, puc); } |