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| author | Richard Henderson <richard.henderson@linaro.org> | 2020-09-05 13:13:10 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2021-06-04 11:50:11 -0700 |
| commit | 31d366390cc4316e55362d40cfc52542d6eea5ab (patch) | |
| tree | 0e01e20a6e7375c9a0dee9177925022d0af0b8cc /trace/mem-internal.h | |
| parent | f2b46c7162f86b05bbc05f1728b1d2a0e6a9e457 (diff) | |
| download | qemu-31d366390cc4316e55362d40cfc52542d6eea5ab.zip qemu-31d366390cc4316e55362d40cfc52542d6eea5ab.tar.gz qemu-31d366390cc4316e55362d40cfc52542d6eea5ab.tar.bz2 | |
tcg/arm: Implement TCG_TARGET_HAS_shv_vec
The three vector shift by vector operations are all implemented via
expansion. Therefore do not actually set TCG_TARGET_HAS_shv_vec,
as none of shlv_vec, shrv_vec, sarv_vec may actually appear in the
instruction stream, and therefore also do not appear in tcg_target_op_def.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'trace/mem-internal.h')
0 files changed, 0 insertions, 0 deletions