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authorFabien Chouteau <chouteau@adacore.com>2011-01-24 12:56:53 +0100
committerBlue Swirl <blauwirbel@gmail.com>2011-01-24 20:54:34 +0000
commit3f10bcbb647372f888a9e34f428eb6f0225c38ca (patch)
tree3a3d1fd89edfb8c8653dfa3ba85eb032b8ec3817 /trace-events
parent0f3a4a01ebafe93055069418c9d65cc7b1493b41 (diff)
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SPARC: Emulation of GRLIB IRQMP
This device exposes two parameters: - set_pil_in (ptr) : A function to set the pil_in of the SPARC CPU - set_pil_in_opaque (ptr) : Opaque argument of the set_pil_in function Emulation of GrLib devices is base on the GRLIB IP Core User's Manual: http://www.gaisler.com/products/grlib/grip.pdf Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'trace-events')
-rw-r--r--trace-events6
1 files changed, 6 insertions, 0 deletions
diff --git a/trace-events b/trace-events
index 3761fd1..832b561 100644
--- a/trace-events
+++ b/trace-events
@@ -234,3 +234,9 @@ disable grlib_gptimer_hit(int id) "timer:%d HIT"
disable grlib_gptimer_readl(int id, const char *s, uint32_t val) "timer:%d %s 0x%x"
disable grlib_gptimer_writel(int id, const char *s, uint32_t val) "timer:%d %s 0x%x"
disable grlib_gptimer_unknown_register(const char *op, uint64_t val) "%s unknown register 0x%"PRIx64""
+
+# hw/grlib_irqmp.c
+disable grlib_irqmp_check_irqs(uint32_t pend, uint32_t force, uint32_t mask, uint32_t lvl1, uint32_t lvl2) "pend:0x%04x force:0x%04x mask:0x%04x lvl1:0x%04x lvl0:0x%04x\n"
+disable grlib_irqmp_ack(int intno) "interrupt:%d"
+disable grlib_irqmp_set_irq(int irq) "Raise CPU IRQ %d"
+disable grlib_irqmp_unknown_register(const char *op, uint64_t val) "%s unknown register 0x%"PRIx64""